US4341960A
Expired / Lapsed
US
⏱️ 0.0 years remaining
I2 L Static shift register
Assignee: Arris Technology Inc
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Filing: 1980-02-21
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Granted: 1982-07-27
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Expires: 2000-02-21
Abstract
Abstract Each bit of the register includes a plurality of active elements which perform as NOR logic gates. Each active element comprises an I 2 L unit consisting of a bipolar inverter transistor and a bipolar injector transistor. Each element is cross-coupled with the previous element and the subsequent element, resulting in the static characteristic of the register. Data transfer control signals are generated which consist of a number of time synchronized pulse trains. Each pulse train is applied to a different one of the active elements in a bit and serves to energize same when positive (high). The shift register is bi-directional. The direction of data transfer is determined solely by the sequence of the data transfer control signals. The register is reset by causing all components of the control signal to simultaneously go low and thereafter restarting same in the proper sequence.
Inventors
- 👤 Kenneth L. Naiff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 23:38
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/28
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
239 words
An I 2 L shift register comprising a bit, said bit comprising a given number of units operably interconnected in sequence, each unit comprising a control input, a data input, a data output, a feedback output, an injector transistor having a collector, a base and an emitter and an inverter transistor having a base, first and second collectors and an emitter, said emitter of said injector transistor being operably connected to said control input, said base of said injector being operably connected to ground, said collector of said injector transistor being operably connected to said base of said inverter transistor, said base of said inverter transistor being operably connected to the data output from the previous unit and the feedback output from the subsequent unit, said first and second collectors of said inverter transistor being operably connected to said data output and feedback output, respectively, and means for generating a series of control signals, one for each unit in the bit, said generating means having separate outputs, each of which is operably connected to said control input of a different one of said units in the bit, said register further comprising control reset means operably connected to said control signal generating means for causing said control signal generating means to temporarily cease generating control signals for a time longer than the decay time of the charge on said bases of said inverter transistors thereby automatically resetting said shift register.
Claim 2
Dependent Claim
239 words
An I 2 L shift register comprising a bit, said bit comprising a given number of units operably interconnected in sequence, each unit comprising a control input, a data input, a data output, a feedback output, an injector transistor having a collector, a base and an emitter and an inverter transistor having a base, first and second collectors and an emitter, said emitter of said injector transistor being operably connected to said control input, said base of said injector being operably connected to ground, said collector of said injector transistor being operably connected to said base of said inverter transistor, said base of said inverter transistor being operably connected to the data output from the previous unit and the feedback output from the subsequent unit, said first and second collectors of said inverter transistor being operably connected to said data output and feedback output, respectively, and means for generating a series of control signals, one for each unit in the bit, said generating means having separate outputs, each of which is operably connected to said control input of a different one of said units in the bit, said register further comprising control reset means operably connected to said control signal generating means for causing said control signal generating means to temporarily cease generating control signals for a time longer than the decay time of the charge on said bases of said inverter transistors thereby automatically resetting said shift register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-07-26 | 1986-01-25 | 1986-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-07-26 | 1990-01-25 | 1990-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-07-26 | 1994-01-25 | 1994-07-27 | $7700.00 | Window Closed / Lapsed |