US3989957A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Count-of-ten semiconductor structure
Assignee: Signetics Corp
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Filing: 1975-10-31
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Granted: 1976-11-02
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Expires: 1995-10-31
Abstract
Abstract A count of ten divider uses plural divide-by-two circuits, plural NOR gates and an inverter formed in a semiconductor body all of the foregoing being in a collector-up configuration.
Inventors
- 👤 Patrick A. Tuccu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:29
CPC Classifications
H; H03; H03K; H03K21/00; H03K21/38; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H10; H10D; H10D84/00; H10D84/60; H10D84/65
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
259 words
In a count-by-ten divider of the type having an input and an output and utilizing plural divide-by-two circuits, plural NOR gates and an inverter, the divider comprising, first, second, third, and fourth divide-by-two logic circuits each having signal input, signal output and signal complement output terminals, first, second, third and fourth NOR gates having first and second input terminals and an output terminal, an inverter having input and output terminals, said first divide-by-two signal input being connected to said divider input, and said signal complement output being connected to the first input of said first NOR gate and the second input of said second NOR gate, said output of said first NOR gate being connected to the signal input of said second divide-by-two circuit and the signal output of said second divide-by-two circuit being connected to the signal input of the third divide-by-two circuit, said third divide-by-two signal output being connected to the second input of the third NOR gate and the first input of the fourth NOR gate, said output of said fourth NOR gate being connected to the inverter input with the inverter output connected to the signal input of said fourth divide-by-two circuit, said fourth divide-by-two signal complement output being connected to the first input of the third NOR gate and the first input of the second NOR gate, the output of said third NOR gate being connected to the second input of said first NOR gate, and the output of said second NOR gate being connected to the second input to said fourth NOR gate.
Claim 2
Dependent Claim
259 words
In a count-by-ten divider of the type having an input and an output and utilizing plural divide-by-two circuits, plural NOR gates and an inverter, the divider comprising, first, second, third, and fourth divide-by-two logic circuits each having signal input, signal output and signal complement output terminals, first, second, third and fourth NOR gates having first and second input terminals and an output terminal, an inverter having input and output terminals, said first divide-by-two signal input being connected to said divider input, and said signal complement output being connected to the first input of said first NOR gate and the second input of said second NOR gate, said output of said first NOR gate being connected to the signal input of said second divide-by-two circuit and the signal output of said second divide-by-two circuit being connected to the signal input of the third divide-by-two circuit, said third divide-by-two signal output being connected to the second input of the third NOR gate and the first input of the fourth NOR gate, said output of said fourth NOR gate being connected to the inverter input with the inverter output connected to the signal input of said fourth divide-by-two circuit, said fourth divide-by-two signal complement output being connected to the first input of the third NOR gate and the first input of the second NOR gate, the output of said third NOR gate being connected to the second input of said first NOR gate, and the output of said second NOR gate being connected to the second input to said fourth NOR gate.
Claim 3
Dependent Claim
78 words
A divider as in claim 1 where at least some of said logic circuits and NOR gates are implemented in integrated injection logic (I 2 L) and including current starving means associated with at least one predetermined node of said divider and comprising, an NPN I 2 L transistor, a lateral PNP current injection transistor, the emitter of said PNP transistor being effectively offset from the base of said NPN transistor to reduce the amount of injection current.
Claim 4
Dependent Claim
24 words
A divider as in claim 2 where two of said nodes include current starving means for introducing delays to prevent a signal race condition.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-11-02 | 1980-05-03 | 1980-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-11-02 | 1984-05-03 | 1984-11-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-11-02 | 1988-05-03 | 1988-11-02 | $7700.00 | Window Closed / Lapsed |