US5030860A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Darlington BiCMOS driver circuit
Assignee: Texas Instruments Inc
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Filing: 1989-11-27
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Granted: 1991-07-09
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Expires: 2009-11-27
Abstract
Abstract A driver circuit is provided which offers decreased input loading, increased output loading, and a high voltage output level corresponding to a logic-1. These results are achieved through the use of pull-up transistors and capacitive and resitive circuitry which allow bootstrapped voltages.
Inventors
- 👤 Hiep V. Tran
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:45
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/013; H03K19/0133; H03K19/0136; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
105 words
A NOR gate driver circuit comprising: an input; a NOR gate connected to said input; a first inverter coupled to said input and connected to a first bipolar pull-up transistor including a parasitic capacitance between the base and emitter of the latter; a second bipolar pull-up transistor connected to said first bipolar pull-up transistor; and a resistance path provided within said first inverter capable of permitting said parasitic capacitor to boot said base of said first bipolar pull-up transistor above the driver supply voltage so as to raise the emitter voltage of said first bipolar pull-up transistor to substantially the level of the supply voltage.
Claim 2
Dependent Claim
105 words
A NOR gate driver circuit comprising: an input; a NOR gate connected to said input; a first inverter coupled to said input and connected to a first bipolar pull-up transistor including a parasitic capacitance between the base and emitter of the latter; a second bipolar pull-up transistor connected to said first bipolar pull-up transistor; and a resistance path provided within said first inverter capable of permitting said parasitic capacitor to boot said base of said first bipolar pull-up transistor above the driver supply voltage so as to raise the emitter voltage of said first bipolar pull-up transistor to substantially the level of the supply voltage.
Claim 3
Dependent Claim
20 words
A NOR gate driver circuit as recited in claim 1 wherein said NOR gate comprises two series connected P-channel transistors.
Claim 4
Dependent Claim
105 words
An AND gate driver circuit comprising: and input; and AND gate connected to said input; a first inverter coupled to said input and connected to a first bipolar pull-up transistor including a parasitic capacitance between the base and emitter of the latter; a second bipolar pull-up transistor connected to said first bipolar pull-up transistor; and a resistance path provided within said first inverter capable of permitting said parasitic capacitor to boot said base of said first bipolar pull-up transistor above the driver supply voltage so as to raise the emitter voltage of said first bipolar pull-up transistor to substantially the level of the supply voltage.
Claim 5
Dependent Claim
105 words
An AND gate driver circuit comprising: and input; and AND gate connected to said input; a first inverter coupled to said input and connected to a first bipolar pull-up transistor including a parasitic capacitance between the base and emitter of the latter; a second bipolar pull-up transistor connected to said first bipolar pull-up transistor; and a resistance path provided within said first inverter capable of permitting said parasitic capacitor to boot said base of said first bipolar pull-up transistor above the driver supply voltage so as to raise the emitter voltage of said first bipolar pull-up transistor to substantially the level of the supply voltage.
Claim 6
Dependent Claim
105 words
A NAND gate driver circuit comprising: an input; a NAND gate connected to said input; a first inverter coupled to said input and connected to a first bipolar pull-up transistor including a parasitic capacitance between the base and emitter of the latter; a second bipolar pull-up transistor connected to said first bipolar pull-up transistor; and a resistance path provided within said first inverter capable of permitting said parasitic capacitor to boot said base of said first bipolar pull-up transistor above the driver supply voltage so as to raise the emitter voltage of said first bipolar pull-up transistor to substantially the level of the supply voltage.
Claim 7
Dependent Claim
105 words
A NAND gate driver circuit comprising: an input; a NAND gate connected to said input; a first inverter coupled to said input and connected to a first bipolar pull-up transistor including a parasitic capacitance between the base and emitter of the latter; a second bipolar pull-up transistor connected to said first bipolar pull-up transistor; and a resistance path provided within said first inverter capable of permitting said parasitic capacitor to boot said base of said first bipolar pull-up transistor above the driver supply voltage so as to raise the emitter voltage of said first bipolar pull-up transistor to substantially the level of the supply voltage.
Claim 8
Dependent Claim
105 words
An OR gate driver circuit comprising: and input; an OR gate connected to said input; a first inverter coupled to said input and connected to a first bipolar pull-up transistor including a parasitic capacitance between the base and emitter of the latter; a second bipolar pull-up transistor connected to said first bipolar pull-up transistor; and a resistance path provided within said first inverter capable of permitting said parasitic capacitor to boot said base of said first bipolar pull-up transistor above the driver supply voltage so as to raise the emitter voltage of said first bipolar pull-up transistor to substantially the level of the supply voltage.
Claim 9
Dependent Claim
105 words
An OR gate driver circuit comprising: and input; an OR gate connected to said input; a first inverter coupled to said input and connected to a first bipolar pull-up transistor including a parasitic capacitance between the base and emitter of the latter; a second bipolar pull-up transistor connected to said first bipolar pull-up transistor; and a resistance path provided within said first inverter capable of permitting said parasitic capacitor to boot said base of said first bipolar pull-up transistor above the driver supply voltage so as to raise the emitter voltage of said first bipolar pull-up transistor to substantially the level of the supply voltage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-08 | 1995-01-07 | 1995-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-08 | 1999-01-07 | 1999-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-08 | 2003-01-07 | 2003-07-09 | $7700.00 | Window Closed / Lapsed |