Patent US5027189A successfully refreshed from Google Patents.
US5027189A
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Integrated circuit solder die-attach design and method
Assignee: Raytheon Co
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Filing: 1990-01-10
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Granted: 1991-06-25
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Expires: 2010-01-10
Abstract
Abstract An improved semiconductor device adapted to be metallurgically bonded to a substrate is disclosed. In particular, monolithic microwave integrated circuit (MMIC) device (10) includes a semiconductor wafer (12) having first and second major surfaces and defining at least one via (34) extending therethrough. An electrical circuit is disposed on the first surface of semiconductor wafer (12). In accordance with this invention, MMIC device (10) includes a ground-plane metallization system (32) provided on the second surface of the semiconductor wafer (12). Backside metallization system (32) promotes preferential "de-wetting" of solder within vias (34) to reduce solder failures associated with die-attach processing. Backside metallization systems (32) includes a ground-plane layer (36) and a second layer (38) fabricated from a non-wettable material which is deposited within via (34). Third layer (42) is deposited on second layer (36) but terminates adjacent a peripheral edge of via (34). Third layer (42) promotes wetting outside via (34) during solder die-attach processing.
Inventors
- 👤 Michael J. Shannon
- 👤 Randolf C. Turnidge
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:12
CPC Classifications
H; H10; H10W; H10W44/00; H10W44/20; H10W20/00; H10W20/20; H10W72/00; H10W72/30; H10W72/90; H10W72/071; H10W72/073; H10W72/07331; H10W72/07336; H10W72/351; H10W72/352; H10W72/50; H10W72/59
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
140 words
A semiconductor device adapted to be metallurgically bonded to a substrate to provide an electrical interconnection therebetween, comprising: a semiconductor wafer having first and second major surfaces, said second major surface defining at least one via extending through said wafer to said first major surface; a ground-plane metallization layer on said second major surface of said semiconductor wafer; first layer means formed on said ground-plane metallization layer at least within said via for preventing bonding of a solder material with said via; said first layer means comprising a layer of a first conductive material formed on the ground-plane metallization layer of said wafer and on the surface of said via; and second layer means formed on a portion of said first layer means and terminating at the peripheral edge of said via for bonding said semiconductor wafer to said substrate.
Claim 2
Dependent Claim
140 words
A semiconductor device adapted to be metallurgically bonded to a substrate to provide an electrical interconnection therebetween, comprising: a semiconductor wafer having first and second major surfaces, said second major surface defining at least one via extending through said wafer to said first major surface; a ground-plane metallization layer on said second major surface of said semiconductor wafer; first layer means formed on said ground-plane metallization layer at least within said via for preventing bonding of a solder material with said via; said first layer means comprising a layer of a first conductive material formed on the ground-plane metallization layer of said wafer and on the surface of said via; and second layer means formed on a portion of said first layer means and terminating at the peripheral edge of said via for bonding said semiconductor wafer to said substrate.
Claim 3
Dependent Claim
40 words
A semiconductor device as in claim 1 wherein said first conductive material is a relatively thin layer of electroplated nickel, said nickel layer deposited on said ground-plane metallization layer of said semiconductor wafer and on said surface of said via.
Claim 4
Dependent Claim
41 words
A semiconductor device as in claim 2 wherein said second layer means comprises a layer of a second conductive material formed on said first conductive material with said layer of second conductive material terminating at the peripheral edge of said via.
Claim 5
Dependent Claim
40 words
A semiconductor device as in claim 3 wherein said second conductive material is a relatively thin layer of metallized gold deposited on and contiguous with said nickel layer, said metallized gold layer terminating adjacent a peripheral edge of said via.
Claim 6
Dependent Claim
38 words
A semiconductor device as in claim 4 wherein said semiconductor wafer is fabricated from gallium arsenide, and wherein said solder material is an electrically conductive metal alloy substantially incapable of wetting on said nickel layer within said via.
Claim 7
Dependent Claim
25 words
A semiconductor device as in claim 5 further comprising a layer of said solder material being formed on and contiguous with said metallized gold layer.
Claim 8
Dependent Claim
150 words
A semiconductor device adapted to be bonded to a substrate, comprising: a semiconductor wafer; an integrated circuit disposed on a first surface of said semiconductor wafer; at least one via extending transversely through said semiconductor wafer from a second surface thereof to said first surface; and a ground-plane layer provided on said semiconductor wafer second surface having a first conductive material deposited on the surface of said via such that said first conductive material interfaces with said integrated circuit, and a second conductive material deposited on said semiconductor wafer second surface adjacent said first conductive material and terminating at a peripheral edge of said via; wherein said first conductive material inhibits wetting of a solder material upon contact with said surface of said via, and said second conductive material permits wetting of said solder material with said ground-plane layer so as to electrically interconnect said semiconductor wafer to said substrate.
Claim 9
Dependent Claim
150 words
A semiconductor device adapted to be bonded to a substrate, comprising: a semiconductor wafer; an integrated circuit disposed on a first surface of said semiconductor wafer; at least one via extending transversely through said semiconductor wafer from a second surface thereof to said first surface; and a ground-plane layer provided on said semiconductor wafer second surface having a first conductive material deposited on the surface of said via such that said first conductive material interfaces with said integrated circuit, and a second conductive material deposited on said semiconductor wafer second surface adjacent said first conductive material and terminating at a peripheral edge of said via; wherein said first conductive material inhibits wetting of a solder material upon contact with said surface of said via, and said second conductive material permits wetting of said solder material with said ground-plane layer so as to electrically interconnect said semiconductor wafer to said substrate.
Claim 10
Dependent Claim
19 words
A semiconductor device according to claim 7 wherein said first conductive material is a barrier plate fabricated from nickel.
Claim 11
Dependent Claim
32 words
A semiconductor device according to claim 8 wherein said nickel barrier plate is electroplated as a continuous layer upon said second surface of said wafer and upon said surface of said via.
Claim 12
Dependent Claim
43 words
A semiconductor device according to claim 7 wherein said first conductive material comprises a relatively thin metallization layer deposited on said second surface of said semiconductor wafer and a relatively thin barrier layer of nickel deposited on and contiguous with said metallization layer.
Claim 13
Dependent Claim
20 words
A semiconductor device according to claim 7 wherein said second conductive material is a relatively thin layer of electroplated gold.
Claim 14
Dependent Claim
24 words
A semiconductor device according to claim 7 wherein said semiconductor wafer is gallium arsenide and said semiconductor device is a microwave integrated circuit device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-24 | 1994-12-24 | 1995-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-24 | 1998-12-24 | 1999-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-24 | 2002-12-24 | 2003-06-25 | $7700.00 | Window Closed / Lapsed |