US5025301A
Expired / Lapsed
US
⏱️ 0.0 years remaining
DRAM which uses MISFETS in the peripheral circuit
Assignee: Hitachi Ltd
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Filing: 1989-04-25
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Granted: 1991-06-18
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Expires: 2009-04-25
Abstract
Abstract A semiconductor integrated circuit device having first and second field-effect transistors, wherein the gate electrode of the first field-effect transistor is defined by a first-level conductor layer, while a wiring which is connected to the source or drain region of the first field-effect transistor is defined by a second-level conductor layer, and the gate electrode of the second field-effect transistor is defined by a combination of the first- and second-level conductor layers which are stacked one upon the other. Further, the respective gate electrodes of the first and second field-effect transistors are formed through respective gate insulator films which are formed on the principal surface of a semiconductor substrate in the same manufacturing step. By virtue of the above-described means, it is possible to reduce the area required for connection between the source or drain region of the first field-effect transistor and the wiring and to thereby increase the scale of integration of the device. In addition, it is possible to lower the resistance of the gate electrode of the second field-effect transistor and to thereby increase the operating speed of the device. Since the first and second field-effect transistors can be formed on a semiconductor substrate having no damage generated thereto, it is possible to increase the dielectric strength of the gate insulator film and to thereby improve the electrical reliability of the device.
Inventors
- 👤 Shinji Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:05
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; H10B10/18; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
250 words
A semiconductor integrated circuit device having a plurality of data lines extending in a row direction, a plurality of word lines extending in a column direcction and a plurality of memory cells connected to the data lines and the word lines, each memory cell comprising a switching transistor element and a capacitor element connected in series; wherein the switching transistor element includes a gate electrode, over a semiconductor substrate, the gate electrode having sides, the transistor element including first and second semiconductor regions arranged at the sides of the gate electrode and extending to a surface of the semiconductor substrate, the first semiconductor region being connected to a data line, and the second semiconductor region connected to said capacitor element; and wherein the device further comprises a first insulating film on said gate electrode in order to isolate said gate electrode from said data lines, wherein said first insulating film has a first insulating film opening, for exposing said first semiconductor region through the first insulating film; a second insulating film on one of the sides of said gate electrode in order to isolate said gate electrode from said data lines, the second insulating film being an insulating film formed by anisotropic etching, the data lines being provided directly in contact with the second insulating film; and a third insulating film, provided on said first insulating film, and having an opening at said first insulating film opening so as to expose the first semiconductor region through the third insulating film
Claim 2
Dependent Claim
250 words
A semiconductor integrated circuit device having a plurality of data lines extending in a row direction, a plurality of word lines extending in a column direcction and a plurality of memory cells connected to the data lines and the word lines, each memory cell comprising a switching transistor element and a capacitor element connected in series; wherein the switching transistor element includes a gate electrode, over a semiconductor substrate, the gate electrode having sides, the transistor element including first and second semiconductor regions arranged at the sides of the gate electrode and extending to a surface of the semiconductor substrate, the first semiconductor region being connected to a data line, and the second semiconductor region connected to said capacitor element; and wherein the device further comprises a first insulating film on said gate electrode in order to isolate said gate electrode from said data lines, wherein said first insulating film has a first insulating film opening, for exposing said first semiconductor region through the first insulating film; a second insulating film on one of the sides of said gate electrode in order to isolate said gate electrode from said data lines, the second insulating film being an insulating film formed by anisotropic etching, the data lines being provided directly in contact with the second insulating film; and a third insulating film, provided on said first insulating film, and having an opening at said first insulating film opening so as to expose the first semiconductor region through the third insulating film
Claim 3
Dependent Claim
21 words
A semiconductor integrated circuit device according to claim 1, wherein said data line is formed directly on said second insulating film.
Claim 4
Dependent Claim
19 words
A semiconductor integrated circuit device according to claim 2, wherein said second insulating film comprises a silicon oxide film.
Claim 5
Dependent Claim
27 words
A semiconductor integrated circuit device according to claim 2, wherein said second insulating film is provided directly on said one of the sides of the gate electrode.
Claim 6
Dependent Claim
26 words
A semiconductor integrated circuit device according to claim 2, wherein said second insulating film is provided on only one of the sides of said gate electrode.
Claim 7
Dependent Claim
38 words
A semiconductor integrated circuit device according to claim 2, further comprising further word lines extending in the column direction and formed over said data lines, with each of said further word lines being connected to said word lines.
Claim 8
Dependent Claim
18 words
A semiconductor integrated circuit device according to claim 6, wherein said further word lines comprise an aluminum layer.
Claim 9
Dependent Claim
34 words
A semiconductor integrated circuit device according to claim 6, wherein said further word lines are made of a conductive material having a smaller resistivity than the material of which said word lines are made.
Claim 10
Dependent Claim
18 words
A semiconductor integrated circuit device according to claim 8, wherein said word lines comprise a polycrystalline silicon layer.
Claim 11
Dependent Claim
25 words
A semiconductor integrated circuit device according to claim 1, wherein said opening in the third insulating film is larger than said first insulating film opening.
Claim 12
Dependent Claim
27 words
A semiconductor integrated circuit device according to claim 1, wherein said second insulating film is provided directly on said one of the sides of the gate electrode.
Claim 13
Dependent Claim
45 words
A semiconductor integrated circuit device according to claim 1, wherein said first insulating film and said second insulating film are in contact with each other such that the data lines, which extend over the first and second insulating films, are isolated from the gate electrode.
Claim 14
Dependent Claim
24 words
A semiconductor integrated circuit device according to claim 1, wherein said first insulating film does not extend along the sides of the gate electrode.
Claim 15
Dependent Claim
26 words
A semiconductor integrated circuit device according to claim 2, wherein said data lines comprise a polycrystalline silicon layer and a silicide layer of refractory metal thereon.
Claim 16
Dependent Claim
35 words
A semiconductor integrated circuit device according to claim 14, further comprising a further insulating film on said data lines and further word lines extending in the column direction ad formed on said further insulating film.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-17 | 1994-12-17 | 1995-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-17 | 1998-12-17 | 1999-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-17 | 2002-12-17 | 2003-06-18 | $7700.00 | Window Closed / Lapsed |