US4475964A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a semiconductor device
Assignee: Toshiba Corp
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Filing: 1983-10-24
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Granted: 1984-10-09
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Expires: 2003-10-24
Abstract
Abstract This invention provides a semiconductor device, which has a high impurity concentration diffusion region such as a drain diffusion region and a resistor comprising a polycrystalline silicon layer (which may be a load of a driver MOS transistor), and in which part of the resistor is in direct contact with the high impurity concentration diffusion region. This invention also provides a method of manufacturing a semiconductor device, which comprises the steps of forming a gate electrode and drain and source diffusion regions along the principal surface of a semiconductor substrate, then forming a polycrystalline silicon resistor layer of a comparatively low impurity concentration such that it is in direct contact with a diffusion region, and subsequently causing impurity diffusion from the diffusion region through thermal treatment to obtain ohmic contact between the diffusion region and resistor layer.
Inventors
- 👤 Syoji Ariizumi
- 👤 Yasushi Fukatsu
- 👤 Fujio Masuoka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:02
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/02; H10D84/03; H10D84/038; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
186 words
A method of manufacturing a semiconductor device, comprising: a step of forming a first polycrystalline silicon layer having a high impurity concentration directly on part of a semiconductor substrate having one conductivity type, said high impurity concentration being of the opposite conductivity type to that of said substrate; a step of forming a diffusion region of impurities having the opposite conductivity type to that of said substrate in and contiguous to the principal surface of said semiconductor substrate by thermally diffusing impurities from said first polycrystalline silicon layer; a step of forming, after a deposition of an insulating layer, a resistor comprising a second polycrystalline silicon layer having lower impurity concentration than that of said first polycrystalline silicon layer in such a manner that one end of the second polycrystalline silicon layer is in direct contact with said first polycrystalline silicon layer; and a step of causing impurity diffusion from said first polycrystalline silicon layer through said one end of said second polycrystalline silicon layer into said second polycrystalline silicon layer by thermal treatment to obtain ohmic contact between said first and second polycrystalline silicon layers.
Claim 2
Independent Claim
186 words
A method of manufacturing a semiconductor device, comprising: a step of forming a first polycrystalline silicon layer having a high impurity concentration directly on part of a semiconductor substrate having one conductivity type, said high impurity concentration being of the opposite conductivity type to that of said substrate; a step of forming a diffusion region of impurities having the opposite conductivity type to that of said substrate in and contiguous to the principal surface of said semiconductor substrate by thermally diffusing impurities from said first polycrystalline silicon layer; a step of forming, after a deposition of an insulating layer, a resistor comprising a second polycrystalline silicon layer having lower impurity concentration than that of said first polycrystalline silicon layer in such a manner that one end of the second polycrystalline silicon layer is in direct contact with said first polycrystalline silicon layer; and a step of causing impurity diffusion from said first polycrystalline silicon layer through said one end of said second polycrystalline silicon layer into said second polycrystalline silicon layer by thermal treatment to obtain ohmic contact between said first and second polycrystalline silicon layers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-10-09 | 1988-04-09 | 1988-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-10-09 | 1992-04-09 | 1992-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-10-09 | 1996-04-09 | 1996-10-09 | $7700.00 | Window Closed / Lapsed |