Self-aligned dielectric assisted planarization process

Claim 1

A method of manufacturing a heterojunction bipolar transistor with substantially isoplanar surfaces, comprising the steps of: providing a semiconductor wafer having a plurality of layers of semiconductor material, said layers forming at least one p-n junction comprising a heterojunction; forming a pattern of photoresist on said wafer, said photoresist pattern having an opening; etching predetermined layers of said semiconductor material through said photoresist opening; depositing dielectric material atop said photoresist and said etched layers of semiconductor material; removing said photoresist and dielectric material deposited thereon; and disposing a thin layer of polymer material atop said wafer and into gaps between said etched layers of semiconductor material and said dielectric material.

Claim 2

A method of manufacturing a heterojunction bipolar transistor with substantially isoplanar surfaces, comprising the steps of: providing a semiconductor wafer having a plurality of layers of semiconductor material, said layers forming at least one p-n junction comprising a heterojunction; forming a pattern of photoresist on said wafer, said photoresist pattern having an opening; etching predetermined layers of said semiconductor material through said photoresist opening; depositing dielectric material atop said photoresist and said etched layers of semiconductor material; removing said photoresist and dielectric material deposited thereon; and disposing a thin layer of polymer material atop said wafer and into gaps between said etched layers of semiconductor material and said dielectric material.

Claim 8

A method of manufacturing a heterojunction bipolar transistor, comprising the steps of: providing a heterojunction bipolar semiconductor wafer having a first layer of a first conductivity type, a second layer of a semiconductor of second conductivity type on the first layer, a third layer of a semiconductor of an opposite conductivity type to the second layer being positioned on the second layer forming a p-n junction, and a fourth layer of a semiconductor of the second conductivity type on the third layer forming a second p-n junction, at least one of the p-n junctions being a heterojunction; forming a photoresist pattern on the wafer with an opening which defines a transistor location; etching the third and fourth layers through an opening in the photoresist pattern down to the second layer and a portion of the second layer toward the first layer; depositing a dielectric material on the second layer through the opening; removing remaining photoresist material and dielectric material deposited thereon from the wafer; depositing a thin layer of polymer on said wafer and into gaps between said dielectric and said second, third, and fourth layers; forming a photoresist pattern on the wafer with a second opening which defines a base location for the heterojunction bipolar transistor; etching the fourth layer through the second opening to the third layer; depositing base contact metal on the third layer through the opening; depositing a second dielectric on the base contact metal and on the sidewalls of the second opening; lifting off the photoresist with overlying second dielectric and metal while maintaining dielectric on the sidewalls; defining a location for emitter contact metal on the fourth layer; depositing emitter contact metal on the emitter contact location; providing a passage through said fourth, third and second layers to the first layer; and depositing collector contact metal on the first layer through the passage.

Claim 9

A method of manufacturing a heterojunction bipolar transistor, comprising the steps of: providing a heterojunction bipolar semiconductor wafer having a first layer of a first conductivity type, a second layer of a semiconductor of second conductivity type on the first layer, a third layer of a semiconductor of an opposite conductivity type to the second layer being positioned on the second layer forming a p-n junction, and a fourth layer of a semiconductor of the second conductivity type on the third layer forming a second p-n junction, at least one of the p-n junctions being a heterojunction; forming a photoresist pattern on the wafer with an opening which defines a transistor location; etching the third and fourth layers through an opening in the photoresist pattern down to the second layer and a portion of the second layer toward the first layer; depositing a dielectric material on the second layer through the opening; removing remaining photoresist material and dielectric material deposited thereon from the wafer; depositing a thin layer of polymer on said wafer and into gaps between said dielectric and said second, third, and fourth layers; forming a photoresist pattern on the wafer with a second opening which defines a base location for the heterojunction bipolar transistor; etching the fourth layer through the second opening to the third layer; depositing base contact metal on the third layer through the opening; depositing a second dielectric on the base contact metal and on the sidewalls of the second opening; lifting off the photoresist with overlying second dielectric and metal while maintaining dielectric on the sidewalls; defining a location for emitter contact metal on the fourth layer; depositing emitter contact metal on the emitter contact location; providing a passage through said fourth, third and second layers to the first layer; and depositing collector contact metal on the first layer through the passage.