US4783238A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Planarized insulation isolation
Assignee: Raytheon Co
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Filing: 1987-07-31
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Granted: 1988-11-08
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Expires: 2007-07-31
Abstract
Abstract A process for fabricating semiconductor integrated circuits which include active regions having well defined mesa structures which maintain their size during processing. Mesa structures are formed in the top portion of a semiconductor substrate, and an insulating layer is formed on the top portion of the semiconductor. Active regions are defined in the semiconductor substrate which include the mesa regions where active devices are to be formed, the remaining regions of the semiconductor substrate being non-active regions. Photoresist is selectively applied on the insulating layer over the non-active regions to maintain exposed insulating layer portions over the mesa structures. The photoresist and the exposed insulating layer portions are etched to thin or remove the exposed insulating layer portions while maintaining the thickness of the covered insulating portions.
Inventors
- 👤 Bruce Roesner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 09:02
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/10; H10W10/17; H10P; H10P95/00; H10P95/06; H10P95/062; H10P95/064; H10W10/01; H10W10/011; H10W10/014; H10W10/0143
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
174 words
A method of processing an integrated circuit which provides for improved planarized insulation isolation, said circuit having a semiconductor substrate with mesa structures in the surface thereof which define active areas therein, said method comprising the steps of: disposing an insulating layer over the surface of said substrate which covers both active and nonactive areas thereof; disposing an undersized photoresist layer over said insulating layer substantially above the nonactive areas of the substrate such that gaps are provided between the undersized photoresist layer and the portions of the insulting layer disposed over the active areas of the substrate; disposing photoresist material in the gaps to form a planarized photoresist layer which extends between the active areas and does not cover the portions of the insulating layer over the active areas; and simultaneously etching the portions of the insulating layer disposed over the active areas and the planarized photoresist layer at a rate which substantially thins the insulating layer portions while maintaining the thickness of the insulating layer over the nonactive areas of the substrate.
Claim 2
Independent Claim
174 words
A method of processing an integrated circuit which provides for improved planarized insulation isolation, said circuit having a semiconductor substrate with mesa structures in the surface thereof which define active areas therein, said method comprising the steps of: disposing an insulating layer over the surface of said substrate which covers both active and nonactive areas thereof; disposing an undersized photoresist layer over said insulating layer substantially above the nonactive areas of the substrate such that gaps are provided between the undersized photoresist layer and the portions of the insulting layer disposed over the active areas of the substrate; disposing photoresist material in the gaps to form a planarized photoresist layer which extends between the active areas and does not cover the portions of the insulating layer over the active areas; and simultaneously etching the portions of the insulating layer disposed over the active areas and the planarized photoresist layer at a rate which substantially thins the insulating layer portions while maintaining the thickness of the insulating layer over the nonactive areas of the substrate.
Claim 3
Dependent Claim
92 words
The method of claim 1 wherein the step of disposing the undersized photoresist layer over the surface of the substrate comprises: depositing photoresist material on the surface of said substrate; rotating said substrate at a relatively slow speed to create a uniform photoresist layer on the surface; rotating said substrate at a higher speed to dry the photoresist layer and remove excess photoresist material; masking said photoresist layer to produce the desired undersized photoresist pattern; exposing said masked photoresist layer; and developing said exposed photoresist layer to produce said undersized photoresist layer.
Claim 4
Dependent Claim
41 words
The method of claim 1 wherein the step of disposing the photoresist material in the gaps comprises: depositing photoresist material on the surface of said substrate; rotating said substrate at a high speed to deposit said photoresist material in the gaps.
Claim 5
Independent Claim
179 words
A method for processing an integrated circuit which provides for improved planarized insulation isolation, said circuit having a semiconductor substrate with mesa structures in the surface thereof which defines active areas therein, said method comprising the steps of: disposing an insulating layer over the surface of said substrate which covers both active and nonactive areas thereof; disposing an undersized photoresist layer over said insulating layer substantially above the nonactive areas of the substrate such that gaps are provided between the undersized photoresist layer and the portions of the insulating layer disposed over the active areas of the substrate; disposing photoresist material in the gaps to form a planarized photoresist layer which extends between the active areas and does not cover the portions of the insulating layer over the active areas which remain exposed; and simultaneously etching the portions of the insulating layer disposed over the active areas and the planarized photoresist layer at a rate which substantially exposes the surface of the mesa structures while maintaining the thickness of the insulating layer over the nonactive areas of the substrate.
Claim 6
Independent Claim
179 words
A method for processing an integrated circuit which provides for improved planarized insulation isolation, said circuit having a semiconductor substrate with mesa structures in the surface thereof which defines active areas therein, said method comprising the steps of: disposing an insulating layer over the surface of said substrate which covers both active and nonactive areas thereof; disposing an undersized photoresist layer over said insulating layer substantially above the nonactive areas of the substrate such that gaps are provided between the undersized photoresist layer and the portions of the insulating layer disposed over the active areas of the substrate; disposing photoresist material in the gaps to form a planarized photoresist layer which extends between the active areas and does not cover the portions of the insulating layer over the active areas which remain exposed; and simultaneously etching the portions of the insulating layer disposed over the active areas and the planarized photoresist layer at a rate which substantially exposes the surface of the mesa structures while maintaining the thickness of the insulating layer over the nonactive areas of the substrate.
Claim 7
Dependent Claim
188 words
A process for fabricating an integrated circuit comprising the steps of: forming mesa structures in the top surface of a semiconductor substrate; forming an insulating layer on the top surface of the semiconductor substrate; defining active regions in the semiconductor substrate including the mesa regions where active devices are to be formed, the remaining regions of the semiconductor substrate being nonactive regions; forming an undersized photoresist layer on the insulating layer over the nonactive regions except in the proximity of the active regions such that gaps are formed between the undersized photoresist layer and the portions of the insulating layer disposed over the mesa structures; depositing planarizing photoresist material in the gaps to form a planarized photoresist layer which comprises the undersized photoresist layer and the planarizing photoresist material and which does not cover the portions of the insulating layer disposed over the mesa structures; and etching the planarized photoresist layer and the portions of the insulating layer disposed over the mesa structures to thin the insulating layer portions disposed over the mesa structures while maintaining the thickness of the insulating layer covered by the planarized photoresist layer.
Claim 8
Dependent Claim
188 words
A process for fabricating an integrated circuit comprising the steps of: forming mesa structures in the top surface of a semiconductor substrate; forming an insulating layer on the top surface of the semiconductor substrate; defining active regions in the semiconductor substrate including the mesa regions where active devices are to be formed, the remaining regions of the semiconductor substrate being nonactive regions; forming an undersized photoresist layer on the insulating layer over the nonactive regions except in the proximity of the active regions such that gaps are formed between the undersized photoresist layer and the portions of the insulating layer disposed over the mesa structures; depositing planarizing photoresist material in the gaps to form a planarized photoresist layer which comprises the undersized photoresist layer and the planarizing photoresist material and which does not cover the portions of the insulating layer disposed over the mesa structures; and etching the planarized photoresist layer and the portions of the insulating layer disposed over the mesa structures to thin the insulating layer portions disposed over the mesa structures while maintaining the thickness of the insulating layer covered by the planarized photoresist layer.
Claim 9
Dependent Claim
22 words
The process of claim 5 wherein the step of forming an insulating layer includes the step of chemically depositing said insulating layer.
Claim 10
Dependent Claim
21 words
The process of claim 6 wherein said step of chemically depositing includes the step of chemical vapor depositing an oxide layer.
Claim 11
Dependent Claim
88 words
The process of claim 5 wherein the step of forming an undersized photoresist layer includes the steps of: depositing photoresist material on the insulating layer; rotating the substrate at a relatively slow speed to provide a uniform photoresist coating over the insulating layer; rotating the substrate at a higher speed to remove excess photoresist material and to dry the photoresist; applying a mask to the photoresist coating to produce the desired undersized photoresist pattern; and exposing and developing the masked photoresist coating to produce the undersized photoresist layer.
Claim 12
Dependent Claim
60 words
The process of claim 8 wherein the step of forming a planarizing photoresist layer includes the steps of: depositing photoresist material on the undersized photoresist layer and the exposed insulating layer; rotating the substrate at a high speed to deposit the photoresist material in the gaps between the undersized photoresist layer and the insulating layer disposed over the mesa structures.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-08 | 1992-05-09 | 1992-11-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-08 | 1996-05-09 | 1996-11-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-08 | 2000-05-09 | 2000-11-08 | $7700.00 | Window Closed / Lapsed |