Semiconductor memory device

Claim 2

A semiconductor memory device having a memory cell array of a folded bit line configuration, comprising a semiconductor substrate, memory cells, two each of which are formed to share a contact hole and surrounded by a trench with an isolation layer at the bottom of the trench, said memory cells including a transistor formed in a semiconductor substrate and having a pair of source/drain regions and a channel with two sides, and data charge storage capacitance means having one electrode formed on the entire sidewall of said trench except a part of said trench where an isolation oxide film is formed on the sidewall of said trench, the isolation oxide film separating the two memory cells from each other, word lines, one word line passing through a region for one bit memory cell, and bit lines, two bit lines passing through a region for one bit memory cell, wherein an isolation oxide film is provided on the two sides of the channel of the transistor.

Claim 3

A semiconductor memory device having a memory cell array of a folded bit line configuration, comprising; a semiconductor substrate, memory cells arranged generally in rows and columns to form a matrix, each memory cell comprising a transfer gate and a data charge storage capacitor, the transfer gate being formed of a transistor formed in said substrate and having a pair of source/drain regions and a channel with two sides, word lines extending in parallel with each other and in a first direction, and passing over the channels of the transistors, bit lines extending in parallel with each other and in a second direction substantially orthogonal to the first direction, every two bit lines adjacent to each other forming a folded bit line pair, every two memory cells adjacent to each other forming a pair of memory cells sharing a contact hole for connection with a bit line, the memory cell pair being arranged in lines parallel with the word lines, with the transistors of first memory cells of the respective memory cell pairs in a memory cell pair line having its channel positioned under one of the word lines to be controlled by it, and transistors of second memory cells of the respective memory cell pairs in the same memory cell pair lines having its channel positioned under another word line adjacent to said one of the word lines, to be controlled by said another word line, the memory cell pair lines adjacent to each other being separated by trenches with an isolation layer at the bottom of said trench, and memory cell pairs adjacent to each other in the same memory cell pair line being separated from each other by trenches with an isolation layer at the bottom of the trench, so that each of the memory cell pairs are surrounded by trenches with an isolation layer at the bottom of the trench, said data charge storage capacitor of each memory cell having electrodes formed on the entirety of the sidewalls of the trench surrounding the memory cell pair except a part of said trench where an isolation oxide film is formed on the sidewall of said trench, the isolation oxide film separating the two memory cells from each other; and wherein an isolation oxide film is provided on the two sides of the channel of the transistor.

Claim 4

A semiconductor memory device having a memory cell array of a folded bit line configuration, comprising; a semiconductor substrate, memory cells arranged generally in rows and columns to form a matrix, each memory cell comprising a transfer gate and a data charge storage capacitor, the transfer gate being formed of a transistor formed in said substrate and having a pair of source/drain regions and a channel with two sides, word lines extending in parallel with each other and in a first direction, and passing over the channels of the transistors, bit lines extending in parallel with each other and in a second direction substantially orthogonal to the first direction, every two bit lines adjacent to each other forming a folded bit line pair, every two memory cells adjacent to each other forming a pair of memory cells sharing a contact hole for connection with a bit line, the memory cell pair being arranged in lines parallel with the word lines, with the transistors of first memory cells of the respective memory cell pairs in a memory cell pair line having its channel positioned under one of the word lines to be controlled by it, and transistors of second memory cells of the respective memory cell pairs in the same memory cell pair lines having its channel positioned under another word line adjacent to said one of the word lines, to be controlled by said another word line, the memory cell pair lines adjacent to each other being separated by trenches with an isolation layer at the bottom of said trench, and memory cell pairs adjacent to each other in the same memory cell pair line being separated from each other by trenches with an isolation layer at the bottom of the trench, so that each of the memory cell pairs are surrounded by trenches with an isolation layer at the bottom of the trench, said data charge storage capacitor of each memory cell having electrodes formed on the entirety of the sidewalls of the trench surrounding the memory cell pair except a part of said trench where an isolation oxide film is formed on the sidewall of said trench, the isolation oxide film separating the two memory cells from each other; and wherein an isolation oxide film is provided on the two sides of the channel of the transistor.

Claim 5

A device according to claim 2, wherein the data charge storage capacitor of one of the memory cells of each memory cell pair is separated from the data charge storage capacitor of the other memory cell of the memory cell pair by an isolation oxide film .

Claim 6

A device according to claim 2, wherein the channel of the transistor of each memory cell is separated from the data charge storage capacitor by an isolation oxide film between the channel and said trench.

Claim 7

A device according to claim 2, wherein the data charge storage capacitor comprises a first electrode formed of a heavily diffused region on the sidewalls of said trenches, an insulating film formed on the heavily diffused region of said trenches, and a second electrode formed of a poly-silicon layer, on the insulating film.

Claim 8

A device according to claim 2, wherein the memory cells of the memory cell pairs in one of the memory cell pair lines are connected to alternate bit lines, and the memory cell pairs in adjacent memory cell pair lines are connected to the interleaving bit lines.

Claim 9

A device according to claim 2, wherein a bit line connected to memory cells in a memory cell pair line passes over said trenches separating adjacent memory cell pairs from each other in adjacent memory cell lines.

Claim 10

A device according to claim 2, wherein the memory cell pairs in one of the memory cell pair lines are offset with respect to the memory cell pairs in another memory cell pair line adjacent to said one of the memory cell pair lines, by an interval between the successive memory cell pairs in the same cell pair line so that said trenches separating memory cell pairs in the same cell pair line are in alignment with the center, in the direction of the word lines, of the memory cell pairs in the adjacent cell pair line.

Claim 11

A device according to claim 2, wherein said trenches separating the adjacent memory cell pairs in the same memory cell pair line extend in the direction of the bit lines.

Claim 12

A device according to claim 2, wherein said trenches separating from each other the adjacent memory cell lines extend in the direction of the word lines.

Claim 13

A device according to claim 1, wherein pairs of parallel bit lines are provided and each pair of bit lines are connected at one end thereof to a sense amplifier.

Claim 14

A device according to claim 11, wherein each of the sense amplifiers comprises a flip-flop circuit having first and second data nodes, and said each pair of the bit lines are connected at one end thereof to said first and second data nodes of the sense amplifier.

Claim 15

A device according to claim 1, wherein the isolation oxide film electrically isolate, from each other, said ones of the electrodes of said data charge storage capacitance means of the pair of memory cells sharing a contact hole.

Claim 16

A device according to claim 1, wherein the bit lines are connected to one of the source/drain regions of said transistor.

Claim 17

A device according to claim 2, wherein each pair of bit lines are connected at one end thereof to a sense amplifier.

Claim 18

A device according to claim 15, wherein each of the sense amplifiers comprises a flip-flop circuit having first and second data nodes, and said each pair of the bit lines are connected at one end thereof to said first and said second data nodes of the sense amplifier.

Claim 19

A device according to claim 2, wherein the isolation oxide film electrically isolates, from each other, said ones of the electrodes of said data charge storage capacitor of the pair of memory cells sharing a contact hole.

Claim 20

A device according to claim 2, wherein the bit lines are connected to one of the source/drain regions of said transistor.

Claim 21

A device according to claim 3, wherein the data charge storage capacitor of one of the memory calls of each memory cell pair is separated from the data charge storage capacitor of the other memory cell of the memory cell pair also by an impurity diffused layer formed on the sidewalls of said trenches.

Claim 22

A device according to claim 4, wherein the channel of the transistor of each memory cell is separated from the data charge storage capacitor also by an impurity diffused layer formed on a flat part of the substrate between the channel and said trench.

Claim 23

A device according to claim 6, wherein the memory cell pairs in one of the memory cell pair lines are offset with respect to the memory cell pairs in another memory cell pair line adjacent to said one of the memory cell pair lines, by half an interval between the successive memory cell pairs in the same cell pair line, so that said trench separating memory cell pairs in the same cell pair line are in alignment with the bit line connected to the memory cell pair in the adjacent cell pair line.