Sense amplifier for high performance dram

Claim 1

A sense amplifier and high performance DRAM, in combination, comprising: a DRAM comprising: at least one row of memory cells (1), whereby the memory cells of the row may be arranged in respective columns with memory cells of other rows; first and second bit lines (BL and BL) successively along the row axially; a fixed voltage source; each of the memory cells comprising a transistor (10, 11, 12, 13) and a capacitor (14, 15, 16, 17) connected serially between one of the bit lines and the fixed voltage source; and word lines respectively for the memory cells, each word line being connected to a gate of the transfer of one of the memory cells for activating the memory cell selectively according to row address; and the sense amplifier comprising: a cross-coupled bistable flip-flop (20, 21) connecting the bit lines to each other in the row; a latch transistor (22) connected to the flip-flop for detecting and amplifying a voltage difference between the bit lines; equalization and precharge means (25, 26, 27, φ 5 and V REF ) for equalizing and precharging the bit lines with a reference voltage in response to a clock control signal; transfer means comprising a cross-coupled pair of transistors (28, 29) also connecting the bit lines to each other for transferring a charging voltage to the bit lines; charging means (31, 32, φ 2 , φ 3 and Vcc) connected to the transfer means for supplying a power-supply level voltage under the control of first and second control clock signals; and boosting means connected to the charging means for boosting the power-supply level voltage of the charging means to a higher level charging voltage under the control of a third control clock signal, whereby the storage capacitors of the memory cells are charged to the higher voltage.