High performance dynamic sense amplifier with voltage boost for row address lines

Claim 1

A dynamic semiconductor memory device of the type having an array of rows and columns of one-transistor memory cells at a face of a semiconductor body with each column of cells connected to a column line and sense amplifiers connected to sense nodes for column lines, each memory cell having an access transistor and a storage capacitor for storing a zero-level or a one-level, said one-level having a maximum voltage about that of a supply voltage connected to said device, said device comprising: a pair of cross-coupled transistors for each sense amplifier, each of the cross-coupled transistors having a current path and a control electrode, the current path of each one of the cross-coupled transistors being separately connected between one of the sense nodes and a grounding node, grounding means for coupling the grounding node to a reference potential, means for applying an address voltage to a row line for a selected row of the memory cells in the array at a given time in an operating cycle, said address voltage having a magnitude substantially higher than said supply voltage during at least part of said operating cycle to thereby increase the level of the voltage stored in the storage capacitors of the selected row where a one-level is stored, means for applying a clock voltage to activate said grounding means at a first time subsequent to said given time in said operating cycle, and pull-up means coupled to the column lines to cause the voltage of a column line for which a one-level was stored to be pulled up to about said supply voltage level.