High performance dynamic sense amplifier with active loads

Claim 1

A sense amplifier for a semiconductor memory device of the type having an array of rows and columns of memory cells with each column split into two column line halves and sense amplifiers connected to pairs of sense nodes at the ends of each pair of column line havles, comprising: a pair of cross-coupled driver transistors, a pair of coupling transistors, at least one grounding transistor and a pair of pull-up transistors, each of the transistors having a current path and a control electrode, means connecting the current path of each of the coupling transistors in series with the current path of a separate one of the driver transistors between one of the sense nodes and a grounding node and connecting the current path of said at least one grounding transistor between the grounding node and reference potential, the current paths of the pull-up transistors being connected separately between the sense nodes and a supply of a given voltage level, means for precharging the sense nodes to said voltage level prior to an active operating cycle, means for addressing a selected row of the memory cells in the array at a given time in the beginning of said operating cycle at a voltage of said voltage level, means for applying a clock voltage to turn on said at least one grounding transistor at a first time subsequent to the said given time in the beginning of an active operating cycle, coupling means separately connecting the control electrodes of the pull-up transistors to the sense nodes, the coupling means being conductive only for a given voltage differential during the active operating cycle, means to boost the voltage on the control electrode of one of the pull-up transistors to higher than said voltage level at a time in the active operating cycle just following the second time, means to maintain the voltage on the control electrodes of the coupling transistors at higher than said voltage level prior to the beginning of active operating cycle and shifting the level of said voltage level during the active operating cycle, and means for addressing said selected row of the memory cells at a voltage higher than said voltage level at a time during said active cycle after said first time.