Sense amplifier circuit for a random access memory

Claim 1

In combination with an electronic memory of the type having a plurality of substantially identical memory cells each comprised of one transistor and a charge storage capacitor, where a plurality of such memory cells are connected to a common bit line having an inherent bit line capacitance, an improved sense amplifier comprising: a first and second transistor each having a gate electrode, a drain and a source, said first gate electrode connected to said second drain, forming a reference node, said second gate electrode connected to said first drain forming a signal node; a first control capacitance operatively connected between said signal node and ground; a second control capacitance operatively connected between said reference node and ground, whereby the minimum input signal voltage required to cause said improved sense amplifier to read the binary state "1" is controlled by the magnitudes of said first and second capacitances; charge sensitive means connected to said reference node for selectively rounding said common bit line; and, a third and fourth transistor forming bit line connection means for selectively connecting said signal node and said reference node to said common bit line, each having a gate electrode, a drain and a source, said third and fourth drains connected to said common bit line, said third and fourth sources connected to said signal node and said reference node, respectively, and said third and fourth gate electrodes being disposed for receiving control voltages.