Semiconductor memory device

Claim 2

A semiconductor memory device composed of an array of memory cells and accessible via bit lines and word lines, the bit lines being of folded configuration; said device comprising: memory cells (MCll-MC24) arranged in pairs, the cells of each pair sharing a contact hole (l0) and being surrounded by an isolation trench (l2), the memory cells including data charge storage capacitance means (l5) at least part of which is formed on the entire sidewall of one of the isolation trenches except for a region where an isolation oxide film (2ʹ) is present to separate memory cells, wherein each word line (7a-7d) passes through a region (UR) of one bit memory cell and two bit lines (6a-­6d) pass through a region for one bit memory cell.

Claim 3

A semiconductor memory device composed of an array of memory cells in a folded bit line configuration; said device comprising: memory cells (MCll-MC24) arranged generally in rows and columns to form a matrix, each memory cell comprising a data charge storage capacitor and a transfer gate provided by a channel (ll) of a transistor, word lines (7a-7d) extending parallel to one another in a first direction to pass over the channels (ll) of the transistors, bit lines (6a-6d) extending parallel to one another and in a second direction substantially orthogonal to the first direction with every two adjacent bit lines forming a folded bit line pair; wherein adjacent memory cells are arranged in pairs with the cells of each pair sharing a common contact (l0) for connection with a respective bit lines, the memory cells being arranged in lines parallel to the word lines, with the transistors of first ones of the memory cells of the respective memory cell pairs in a memory cell pair line having channels (ll) positioned under one of the word line (7a-7d) so as to be controlled thereby and the transistors of second memory cells of the respective memory cell pairs in the same memory cell pair line having channels (ll) positioned under another word line adjacent to said one word line, to be controlled thereby and wherein the adjacent memory cell pair lines and the memory cell pairs adjacent to each other in the same memory cell pair line are separated by isolation trenches (l2), so that each pair of memory cells is surrounded by an isolation trench, the data charge storage capacitors (l5) of the memory cells being at least partly formed by capacitors (Cp) on the sidewalls of the isolation trenches (l2) surrounding the pairs of memory cells.

Claim 4

A semiconductor memory device composed of an array of memory cells in a folded bit line configuration; said device comprising: memory cells (MCll-MC24) arranged generally in rows and columns to form a matrix, each memory cell comprising a data charge storage capacitor and a transfer gate provided by a channel (ll) of a transistor, word lines (7a-7d) extending parallel to one another in a first direction to pass over the channels (ll) of the transistors, bit lines (6a-6d) extending parallel to one another and in a second direction substantially orthogonal to the first direction with every two adjacent bit lines forming a folded bit line pair; wherein adjacent memory cells are arranged in pairs with the cells of each pair sharing a common contact (l0) for connection with a respective bit lines, the memory cells being arranged in lines parallel to the word lines, with the transistors of first ones of the memory cells of the respective memory cell pairs in a memory cell pair line having channels (ll) positioned under one of the word line (7a-7d) so as to be controlled thereby and the transistors of second memory cells of the respective memory cell pairs in the same memory cell pair line having channels (ll) positioned under another word line adjacent to said one word line, to be controlled thereby and wherein the adjacent memory cell pair lines and the memory cell pairs adjacent to each other in the same memory cell pair line are separated by isolation trenches (l2), so that each pair of memory cells is surrounded by an isolation trench, the data charge storage capacitors (l5) of the memory cells being at least partly formed by capacitors (Cp) on the sidewalls of the isolation trenches (l2) surrounding the pairs of memory cells.

Claim 5

A device according to claim 2, wherein the data charge storage capacitor (Cp) of one of the memory cells of each memory cell pair which is formed on a sidewall of the associated trench is separated from the data charge storage capacitor (Cp) of the other memory cell of the memory cell pair by an isolation oxide film (2ʹ) formed on the sidewall of the associated trench.

Claim 6

A device according to claim 2 or 3, wherein the channel of the transistor of each memory cell is separated from the data charge storage capacitor thereof by an isolation oxide film formed on a flat part of a substrate between the channel and the isolation trench.

Claim 7

A device according to claim 3 or 4, wherein the isolation film (2ʹ, 2) is supplemented by an impurity diffusion layer (l4).

Claim 12

l0. A device according to any one of claims 2 to 9, wherein the isolation trenches which separate the adjacent memory cell pairs in the same memory cell pair line extend in the direction of the bit lines.