EP0169346A1
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Dynamic memory cell and method for manufacturing the same
Assignee: Toshiba Corp
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Filing: 1985-05-31
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Granted: —
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Expires: 2005-05-31
Abstract
Abstract A first semiconductor layer (43) of a P + type is formed on a semiconductor substrate (41) of a P - type and a mask layer (81) is formed on a portion of the first semiconductor layer (43) other than that area where a capacitor is to be formed. A hole (45) is formed in a direction of a thickness of the first semiconductor layer (43), using the mask layer (81). An N + layer (47) is formed on the inner surface of the hole (45) with the mask layer (81) as a mask. An insulating film (49) for capacitor formation is formed on the inner surface of the resultant hole and on that area of the first semiconductor layer where the resultant dynamic memory cell is electrically separated from an adjacent dynamic memory cell. A conductive layer (53) acting as a capacitor electrode is formed on the capacitor formation insulating film (49). With the conductive layer (53) as a mask, an impurity of an N type is doped into the first semiconductor layer (43) to form a second semiconductor layer (57) of a P type in the surface portion of the first semiconductor layer (43). A MOS transistor is formed in the surface portion of the second conductive layer (57).
Inventors
- 👤 Mitsugi C/O Patent Division Ogura
- 👤 Fujio C/O Patent Division Masuoka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 02:56
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; H10B12/01; H10B12/02; H10B12/03; H10B12/038; Y; Y10; Y10S; Y10S148/00; Y10S148/018
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
217 words
A dynamic memory cell comprising: a capacitor comprised of a semiconductor substrate of a first conductivity type having one major surface and having at least one hole extending in a direction of a thickness in said major surface portion, a semiconductor layer of a second conductivity type formed on the inner surface of the hole of the semiconductor substrate, an insulating layer formed on the inner surface of the semiconductor layer and a conductive layer formed on the inner surface of said insulating layer; a MOS (metal oxide semiconductor) transistor; and means for electrically isolating the memory cell from an adjacent memory cell, characterized in that said semiconductor substrate is comprised of a semiconductor substrate (41) of the first conductivity type, a first conductive layer of the first conductivity type formed on the semiconductor substrate (41), including the hole and having an impurity concentration higher than that of the semiconductor substrate (41); and said electrically isolating means is comprised of an area (51) of the first semiconductor layer (43) which extends between the dynamic memory cell and the adjacent dynamic memory cell and an insulating film (49) for separation which is formed on the extending area (51) and which has a thickness substantially equal to, and smaller than, that of the insulating film (49) for capacitor formation.
Claim 2
Dependent Claim
217 words
A dynamic memory cell comprising: a capacitor comprised of a semiconductor substrate of a first conductivity type having one major surface and having at least one hole extending in a direction of a thickness in said major surface portion, a semiconductor layer of a second conductivity type formed on the inner surface of the hole of the semiconductor substrate, an insulating layer formed on the inner surface of the semiconductor layer and a conductive layer formed on the inner surface of said insulating layer; a MOS (metal oxide semiconductor) transistor; and means for electrically isolating the memory cell from an adjacent memory cell, characterized in that said semiconductor substrate is comprised of a semiconductor substrate (41) of the first conductivity type, a first conductive layer of the first conductivity type formed on the semiconductor substrate (41), including the hole and having an impurity concentration higher than that of the semiconductor substrate (41); and said electrically isolating means is comprised of an area (51) of the first semiconductor layer (43) which extends between the dynamic memory cell and the adjacent dynamic memory cell and an insulating film (49) for separation which is formed on the extending area (51) and which has a thickness substantially equal to, and smaller than, that of the insulating film (49) for capacitor formation.
Claim 3
Dependent Claim
59 words
A dynamic memory cell according to claim 1, further including a second semiconductor layer (57) of the first conductivity type formed in the surface area of said first semiconductor layer (43) and having an impurity concentration lower than that of the first semiconductor layer (43) and in which said MOS transistor is partially formed the second semiconductor layer (57).
Claim 4
Dependent Claim
26 words
A dynamic memory cell according to claim 2, in which the second semiconductor layer (57) is formed in a self-aligned fashion to the conductive layer (53).
Claim 5
Dependent Claim
154 words
A dynamic memory cell according to claim 3, in which said MOS transistor is comprised of a gate insulating film (65) formed on the second semiconductor layer (57) and having a thickness equal to, or thicker than, that of the insulating film (49) for separation; a gate electrode (67) formed on the gate insulating film (65); one electrode (59) of the second conductivity type formed in the second semiconductor layer (57) in a self-aligned fashion to the gate electrode (67) such that it is in contact with the semiconductor layer (47) of a second conductivity type for capacitor formation; the other electrode (63) of the second conductivity type formed in the second semiconductor layer (57) in the self-aligned fashion to the gate electrode (67) such that it is located at a predetermined interval relative to the one electrode (59); and an area (61) located between the electrodes (59, 63) and acting as a gate.
Claim 6
Dependent Claim
77 words
A dynamic memory cell according to claim 3, in which the first semiconductor layer (43) has an impurity concentration of 0.8 x 10 16 cm- 3 to 1.2 x 10 16 c m - 3 , the second semiconductor layer (57) has an impurity concentration of 3 x 10 15 cm - 3 to 7 x 10 15 cm- 3 , and the insulating film for capacitor formation has a thickness of 7 nm to 13 nm.
Claim 7
Independent Claim
229 words
A method of manufacturing a dynamic memory cell comprising the steps of: (a) forming a MOS (metal oxide semiconductor) capacitor; (b) forming a MOS transistor; and (c) forming a separation area for electrically separating a dynamic memory cell, comprised of the MOS capacitor and MOS transistor, from an adjacent dynamic memory cell, characterized in that, said steps (b) and (c) comprise the steps of: forming a first semiconductor layer (43) of a first conductivity type on a semiconductor substrate (41) of the first conductivity type, the first semiconductor layer (43) being higher in impurity concentration than the semiconductor substrate; forming on one major surface portion of the first semiconductor layer a mask (81) for forming at least one hole (45) for capacitor formation; forming the hole (45) in a direction of a thickness of the first semiconductor layer (43) in the one major surface of the layer (43); forming a capacitor formation semiconductor layer (47) of a second conductivity type on the inner surface of the hole with the mask (81) for hole formation as a mask; forming a capacitor formation insulating film (49) on the inner surface of the hole and on that area (51) of the first semiconductor layer (43) which is electrically isolating the dynamic memory cell from the adjacent dynamic memory cell; and forming a capacitor electrode (53) on the capacitor formation insulating film (49).
Claim 8
Independent Claim
229 words
A method of manufacturing a dynamic memory cell comprising the steps of: (a) forming a MOS (metal oxide semiconductor) capacitor; (b) forming a MOS transistor; and (c) forming a separation area for electrically separating a dynamic memory cell, comprised of the MOS capacitor and MOS transistor, from an adjacent dynamic memory cell, characterized in that, said steps (b) and (c) comprise the steps of: forming a first semiconductor layer (43) of a first conductivity type on a semiconductor substrate (41) of the first conductivity type, the first semiconductor layer (43) being higher in impurity concentration than the semiconductor substrate; forming on one major surface portion of the first semiconductor layer a mask (81) for forming at least one hole (45) for capacitor formation; forming the hole (45) in a direction of a thickness of the first semiconductor layer (43) in the one major surface of the layer (43); forming a capacitor formation semiconductor layer (47) of a second conductivity type on the inner surface of the hole with the mask (81) for hole formation as a mask; forming a capacitor formation insulating film (49) on the inner surface of the hole and on that area (51) of the first semiconductor layer (43) which is electrically isolating the dynamic memory cell from the adjacent dynamic memory cell; and forming a capacitor electrode (53) on the capacitor formation insulating film (49).
Claim 9
Dependent Claim
97 words
A method according to claim 6, in which said MOS transistor forming step comprises the steps of: doping an impurity of the second conductivity type in a predetermined surface area of the first semiconductor layer (43) with the capacitor electrode (53) as a mask to form a second semiconductor layer (57) of the first conductivity type in the predetermined surface area of the first semiconductor layer (43), the impurity concentration of the second semiconductor layer (57) being lower than that of the first semiconductor layer (57); and forming the MOS transistor in the second semiconductor layer (57).
Claim 10
Dependent Claim
142 words
A method according to claim 7, in which said transistor forming step comprises the steps of: forming a gate insulating film (65) on the second semiconductor layer (57), the gate insulating film (65) being equal to, or thicker than, the capacitor formation insulating film for separation (49); forming a gate electrode (67) on the gate insulating film (65); and forming one electrode layer (59) of the second conductivity type in the surface area of the second semiconductor layer (57) in a self-aligned fashion relative to said gate electrode (67) and the other electrode layer (63) of the second conductivity type in the second semiconductor layer (57) in a self-aligned fashion relative to the gate electrode (67) with a predetermined interval left with respect to said one electrode layer (59), said one electrode layer (59) being in contact with said semiconductor layer (47).
Claim 11
Dependent Claim
73 words
A method according to claim 8, in which the impurity concentration of said first conductivity layer is 0.8 x 10 16 c m - 3 to 1 . 2 x 10 16 cm- 3 , the impurity concentration of the second semiconductor layer is 3 x 10 15 cm -3 to 7 x 10 15 cm -3 and the thickness of the insulating film for capacitor formation is 7 nm and 13 nm.
References Cited (Backward Citations)
EP0032030A2
Cited
EP0085988A2
Cited
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