EP0234741A2
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Mitsubishi Electric Corp
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Filing: 1987-01-27
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Granted: —
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Expires: 2007-01-27
Abstract
Abstract A semiconductor memory device having a folded bit line structure (16a, 16b), in which a field oxide film (2) is formed on both sides of a channel region (11) of a transfer gate, a groove isolation region 12 for defining a memory cell region is formed to surround the field oxide film 2, and the side walls of the groove isolation region 12 include a memory cell utilized as a capacitor for storing charges as information.
Inventors
- 👤 Kazutami Mitsubishi-Denki K.K. Arimoto
- 👤 Koichiro Mitsubishi-Denki K.K. Mashiko
- 👤 Kiyohiro Mitsubishi-Denki K.K. Furutani
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 09:02
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
169 words
A semiconductor memory device with a folded bit line structure having a pair of complementary bit lines comprised of adjacent two bit lines (16a, 16b), including a plurality of memory cells, each of said memory cells comprising: a transfer gate including a first impurity diffusion region (5a), a second impurity diffusion region (5b), and a channel region (11) formed between said first and second impurity diffusion regions (5a, 5b), a relatively thick insulating film (2) provided on both sides of said channel region (11) which are not connected to said impurity diffusion regions (5a, 5b), and a first capacitor (C F ) formed to surround said relatively thick insulator film and having one electrode (5b) connected to said second impurity diffusion region (5b), a groove isolation region (12) including a groove provided around said first capacitor (C F ) to define said memory cell region, and a second capacitor (C P ) formed on the side walls of said groove isolation region (12) and connected to said first capacitor.
Claim 2
Dependent Claim
169 words
A semiconductor memory device with a folded bit line structure having a pair of complementary bit lines comprised of adjacent two bit lines (16a, 16b), including a plurality of memory cells, each of said memory cells comprising: a transfer gate including a first impurity diffusion region (5a), a second impurity diffusion region (5b), and a channel region (11) formed between said first and second impurity diffusion regions (5a, 5b), a relatively thick insulating film (2) provided on both sides of said channel region (11) which are not connected to said impurity diffusion regions (5a, 5b), and a first capacitor (C F ) formed to surround said relatively thick insulator film and having one electrode (5b) connected to said second impurity diffusion region (5b), a groove isolation region (12) including a groove provided around said first capacitor (C F ) to define said memory cell region, and a second capacitor (C P ) formed on the side walls of said groove isolation region (12) and connected to said first capacitor.
Claim 3
Dependent Claim
18 words
A semiconductor memory device in accordance with claim l, each of said memory cells has an U shape.
Claim 4
Dependent Claim
41 words
A semiconductor memory device in accordance with claim 1, whererin said first impurity diffusion (5a) region is shared with a single adjacent memory cell, whereby two memory cells are both connected to a single bit line through a contact hole (10).
Claim 5
Dependent Claim
85 words
A semicondutor memory device in accordance with claim 1, wherein said second capacitor (C P ) has one electrode connected to one electrode (5b) of said first capacitor (C F ) and the other electrode (3) connected to the other electrode (3) of said first capacitor (C F ), said other electrode (3) of said first capacitor being formed to extend over and beyond said groove isolation region (12) so as to be shared with the first and second capacitors of the adjacent memory cell.
Claim 6
Dependent Claim
64 words
A semiconductor memory device in accordance with claim 1, wherein each of said memory cells further comprises a third capacitor (C S ) which is formed to be overlapped at least with the other electrode (3) of said first capacitor (C F ) through a third insulator film (14) and has one electrode connected to said second impurity diffusion region (5b) at one thereof.
References Cited (Backward Citations)
No citation records indexed.
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