Dram nonvolatizer

Claim 2

An integrated circuit memory controller, comprising: connections for system power supply input, battery input, and power supply output; connections for refresh control signal input and output; switching circuitry which, in a first mode of operation, connects said input power supply connection to said output power supply connection, and connects said refresh control signal input to said refresh control signal output, and, in a second mode of operation, disconnects said input power supply connection from said output power supply connection, and disconnects said refresh control signal input from said refresh control signal output; voltage regulator circuitry which, in said second mode of operation, provides a regulated voltage, derived from said battery input, to said power supply output connections; and refresh control signal generation logic which, in said second mode of operation, provides refresh control signals, with appropriate timing to preserve data in DRAMs of a predetermined type, to said refresh control signal output.

Claim 3

The controller of claim 1, wherein said controller is programmable to define whether refresh control signals are to be applied to said DRAMs if the system power supply fails.

Claim 4

The controller of claim 1, further comprising a bandgap voltage reference, and a monitor circuit which tests the system power supply voltage with reference to said bandgap voltage reference; and wherein, when said monitor circuit detects that the system power supply voltage has declined below a predetermined acceptable range, said monitor circuit can cause said switching circuitry, said voltage regulator circuitry, and said refresh control signal generation logic to change from said first mode to said second mode.

Claim 5

The controller of claim 1, wherein said refresh control signal generation logic comprises a temperature-compensated oscillator, and controls the timing of said refresh control signals with reference to said oscillator.

Claim 6

The integrated circuit memory controller of claim 1, wherein said refresh control signal generation logic does not supply address signals to said DRAM chips with said refresh control signals.

Claim 7

The integrated circuit memory controller of claim 1, wherein said voltage regulator circuitry further comprises a trimmable resistor network.

Claim 8

The integrated circuit memory controller of claim 1, wherein said voltage regulator circuitry operates with at least about 40 mV of hysteresis.

Claim 9

The integrated circuit memory controller of claim 1, wherein said refresh control signal input is connected to receive at least a row-address-strobe signal and a column-address-strobe signal.

Claim 10

The integrated circuit memory controller of claim 1, wherein said refresh control signal input is connected to receive at least a write-enable signal, a row-address-strobe signal, and a column-address-strobe signal.

Claim 11

The integrated circuit memory controller of claim 1, wherein said refresh control signal input is connected to receive at least four signal lines.

Claim 12

A computer system, comprising: at least one input device; at least one output device; at least one processor unit, operatively connected to said input and output devices; a power supply, which provides a system supply voltage on at least one system supply voltage line; at least one battery; and at least one memory subsystem, accessible by said processor unit comprising: a plurality of dynamic random access memories (DRAMs) having input connections to receive refresh control signals and power supply; and a controller; wherein said controller is connected and programmed to connect said system supply voltage line to said power supply connections of said DRAMs under normal operating conditions; wherein said controller is also connected and programmed to receive and regulate the output of said battery to thereby provide a supply voltage output to said power supply connections of said DRAMs when a failure of the system supply voltage occurs; and wherein said controller provides refresh control signals, with appropriate timing, to said DRAMs when a failure of the system supply voltage occurs.

Claim 13

A computer system, comprising: at least one input device; at least one output device; at least one processor unit, operatively connected to said input and output devices; a power supply, which provides a system supply voltage on at least one system supply voltage line; at least one battery; and at least one memory subsystem, accessible by said processor unit comprising: a plurality of dynamic random access memories (DRAMs) having input connections to receive refresh control signals and power supply; and a controller; wherein said controller is connected and programmed to connect said system supply voltage line to said power supply connections of said DRAMs under normal operating conditions; wherein said controller is also connected and programmed to receive and regulate the output of said battery to thereby provide a supply voltage output to said power supply connections of said DRAMs when a failure of the system supply voltage occurs; and wherein said controller provides refresh control signals, with appropriate timing, to said DRAMs when a failure of the system supply voltage occurs.

Claim 14

The system of claim 11, wherein individual ones of said memory subsystems are separately mounted on individual physical modules.

Claim 15

The system of claim 11, wherein individual ones of said memory subsystems, each including at least four said DRAMs, are separately mounted on individual physically separate modules.

Claim 16

The system of claim 11, wherein said DRAM chips do not require externally supplied row addresses for refresh.

Claim 17

The system of claim 11, wherein said DRAM chips are connected to receive row-address-strobe and column-address-strobe signals from said controller, and wherein said DRAM chips are internally configured to begin a refresh cycle upon receiving a column-address-strobe-before-row-address-strobe signal sequence.

Claim 18

The system of claim 11, wherein said controller does not supply address signals to said DRAM chips with said refresh control signals.

Claim 19

The system of claim 11, wherein each of said subsystems includes nine of said DRAMs.

Claim 20

The system of claim 11, wherein individual ones of said subsystems, each including one of said controller chips and nine of said DRAMs, are separately mounted on individual physically separate modules.

Claim 21

The system of claim 11, wherein said battery has an operating voltage which is higher than the highest normal value of the system power supply.

Claim 22

The system of claim 11, further comprising a capacitor connected to said supply voltage output.

Claim 23

The system of claim 11, wherein, immediately upon detection of a power failure, said controller provides a burst of said refresh control signals, including a number sufficient to refresh all rows of said memories, as an output to the memories.

Claim 24

The system of claim 11, wherein said battery has an operating voltage which is higher than the highest normal value of the system power supply, and wherein said controller regulates the output of said battery with reference to a bandgap-voltage reference circuit.

Claim 25

The system of claim 11, wherein, after a power failure has occurred and has ended, said controller provides a continuous series of said refresh control signals as an output to said memories.

Claim 26

The system of claim 11, wherein said controller further comprises connections for refresh control signal input and output, and wherein said refresh control signal input is connected to receive at least four signal lines.

Claim 27

The system of claim 11, wherein said controller further comprises connections for refresh control signal input and output, and wherein said refresh control signal input is connected to receive at least four signal lines, and wherein, when no power failure has been detected, said controller connects said refresh control signal input through to said refresh control signal output.

Claim 28

An integrated circuit memory controller, for connection to a plurality of dynamic random access memories, to a battery, to a system power supply, and to leads for system-generated refresh timing signals, comprising: monitor circuitry, which monitors the absolute level of said system power supply voltage, and generates a failure-detect signal to indicate when the system power supply voltage is no longer within an acceptable range; voltage regulator circuitry which, when the system power supply has departed from said acceptable range, provides a regulated voltage, derived from the battery, as a power supply output to the memories; and refresh control signal generation logic which, when the system power supply has departed from said acceptable range, provides refresh control signals, with appropriate timing to preserve data, as an output to the memories.

Claim 29

An integrated circuit memory controller, for connection to a plurality of dynamic random access memories, to a battery, to a system power supply, and to leads for system-generated refresh timing signals, comprising: monitor circuitry, which monitors the absolute level of said system power supply voltage, and generates a failure-detect signal to indicate when the system power supply voltage is no longer within an acceptable range; voltage regulator circuitry which, when the system power supply has departed from said acceptable range, provides a regulated voltage, derived from the battery, as a power supply output to the memories; and refresh control signal generation logic which, when the system power supply has departed from said acceptable range, provides refresh control signals, with appropriate timing to preserve data, as an output to the memories.

Claim 30

The controller of claim 26, further comprising a bandgap voltage reference; and wherein said monitor circuitry tests the system power supply voltage with reference to a bandgap voltage reference.

Claim 31

The integrated circuit memory controller of claim 26, wherein said refresh control signal generation logic does not supply address signals to said DRAM chips with said refresh control signals.

Claim 32

The integrated circuit memory controller of claim 26, wherein said voltage regulator circuitry further comprises a trimmable resistor network.

Claim 33

The integrated circuit memory controller of claim 26, wherein said voltage regulator circuitry operates with at least about 40 mV of hysteresis.

Claim 34

The integrated circuit memory controller of claim 26, wherein, immediately upon departure of the system power supply from said acceptable range, said refresh control signal generation logic provides a burst of said refresh control signals, including enough of said refresh control signals to refresh all rows of said memories, as an output to the memories.

Claim 35

The integrated circuit memory controller of claim 26, wherein, whenever said monitor circuitry indicates that the system power supply voltage has returned to said acceptable range after having been outside of said acceptable range, said refresh control signal generation logic thereupon begins to provide a continuous series of said refresh control signals as an output to the memories.

Claim 36

An integrated circuit memory controller, for connection to a plurality of dynamic random access memories, to a battery, to a system power supply, and to leads for system-generated refresh timing signals, comprising: monitor circuitry, which monitors the absolute level of said system power supply voltage with reference to a bandgap voltage reference, and generates a failure-detect signal to indicate when the system power supply voltage is no longer within an acceptable range; voltage regulator circuitry which, if power-fail protection has been enabled and the system power supply voltage has departed from said acceptable range, or if power-fail protection has been enabled and the system power supply voltage is within said acceptable range AND a predetermined control signal, which indicates that the system will resume control of the refresh control signals, has not been received since the system power supply voltage returned to said acceptable range, provides a regulated voltage, derived from the battery, to the memories in place of the system supply voltage; and refresh control signal generation logic which, if power-fail protection has been enabled and the system power supply voltage has departed from said acceptable range, or if power-fail protection has been enabled and the system power supply voltage is within said acceptable range AND said predetermined control signal has not been received since the system power supply voltage returned to said acceptable range, provides refresh control signals, with appropriate timing, to the memories in place of the system-generated refresh timing signals.

Claim 37

An integrated circuit memory controller, for connection to a plurality of dynamic random access memories, to a battery, to a system power supply, and to leads for system-generated refresh timing signals, comprising: monitor circuitry, which monitors the absolute level of said system power supply voltage with reference to a bandgap voltage reference, and generates a failure-detect signal to indicate when the system power supply voltage is no longer within an acceptable range; voltage regulator circuitry which, if power-fail protection has been enabled and the system power supply voltage has departed from said acceptable range, or if power-fail protection has been enabled and the system power supply voltage is within said acceptable range AND a predetermined control signal, which indicates that the system will resume control of the refresh control signals, has not been received since the system power supply voltage returned to said acceptable range, provides a regulated voltage, derived from the battery, to the memories in place of the system supply voltage; and refresh control signal generation logic which, if power-fail protection has been enabled and the system power supply voltage has departed from said acceptable range, or if power-fail protection has been enabled and the system power supply voltage is within said acceptable range AND said predetermined control signal has not been received since the system power supply voltage returned to said acceptable range, provides refresh control signals, with appropriate timing, to the memories in place of the system-generated refresh timing signals.

Claim 38

The controller of claim 33, wherein said predetermined control signals comprise a serial stream of more than 16 bits of data.

Claim 39

The integrated circuit memory controller of claim 33, wherein said predetermined control signals comprise more than 16 bits of data on two or more lines.

Claim 40

The integrated circuit memory controller of claim 33, wherein said predetermined control signals comprise more than 16 bits of data on two or more address lines.

Claim 41

The integrated circuit memory controller of claim 33, wherein, if power-fail protection has been enabled and if the system power supply voltage is within said acceptable range and if said predetermined control signal has not been received since the system power supply voltage returned to said acceptable range, said refresh control signal generation logic provides a continuous series of said refresh control signals as an output to the memories.

Claim 42

The integrated circuit memory controller of claim 33, wherein said refresh control signal generation logic does not supply address signals to said DRAM chips with said refresh control signals.

Claim 43

The integrated circuit memory controller of claim 33, wherein said voltage regulator circuitry further comprises a trimmable resistor network.

Claim 44

The integrated circuit memory controller of claim 33, wherein said voltage regulator circuitry operates with at least about 40 mV of hysteresis.

Claim 45

An integrated circuit memory controller, for attachment to a plurality of dynamic random access memories, to a battery, to a system power supply, and to leads for system-generated refresh timing signals, comprising: connections for system power supply input, battery input, and power supply output; connections for refresh control signal input and output; monitor circuitry, which includes a bandgap voltage reference, and which monitors the absolute level of said system power supply voltage, and which generates a failure-detect signal to indicate when the system power supply voltage is no longer within an acceptable range; switching circuitry which, during normal operation, connects said input power supply connection to said output power supply connection, and connects said refresh control signal input to said refresh control signal output, and, when the system power supply has departed from said acceptable range, disconnects said input power supply connection to said output power supply connection, and at least partially disconnects said refresh control signal input from said refresh control signal output; and voltage regulator circuitry which, when the system power supply has departed from said acceptable range, provides a regulated voltage, derived from the battery, to said output power supply connection, and which is configured to operate with at least about 40 mV of hysteresis, and which further comprises a trimmable resistor network; and refresh control signal generation logic which comprises a temperature-compensated oscillator, and which, when the system power supply has departed from said acceptable range, provides refresh control signals, with appropriate timing to preserve data, in DRAMs of a predetermined type, as an output to the memories, wherein said refresh control signal generation logic does not supply address signals to said DRAM chips with said refresh control signals; wherein said refresh control signal input is connected to receive at least four signal lines, including at least a write-enable signal, a row-address-strobe signal, and a column-address-strobe signal; and wherein, whenever said monitor circuitry indicates that the system power supply voltage has returned to said acceptable range after having been outside of said acceptable range, said refresh control signal generation logic thereupon begins to provide a continuous series of said refresh control signals as an output to the memories.

Claim 46

An integrated circuit memory controller, for attachment to a plurality of dynamic random access memories, to a battery, to a system power supply, and to leads for system-generated refresh timing signals, comprising: connections for system power supply input, battery input, and power supply output; connections for refresh control signal input and output; monitor circuitry, which includes a bandgap voltage reference, and which monitors the absolute level of said system power supply voltage, and which generates a failure-detect signal to indicate when the system power supply voltage is no longer within an acceptable range; switching circuitry which, during normal operation, connects said input power supply connection to said output power supply connection, and connects said refresh control signal input to said refresh control signal output, and, when the system power supply has departed from said acceptable range, disconnects said input power supply connection to said output power supply connection, and at least partially disconnects said refresh control signal input from said refresh control signal output; and voltage regulator circuitry which, when the system power supply has departed from said acceptable range, provides a regulated voltage, derived from the battery, to said output power supply connection, and which is configured to operate with at least about 40 mV of hysteresis, and which further comprises a trimmable resistor network; and refresh control signal generation logic which comprises a temperature-compensated oscillator, and which, when the system power supply has departed from said acceptable range, provides refresh control signals, with appropriate timing to preserve data, in DRAMs of a predetermined type, as an output to the memories, wherein said refresh control signal generation logic does not supply address signals to said DRAM chips with said refresh control signals; wherein said refresh control signal input is connected to receive at least four signal lines, including at least a write-enable signal, a row-address-strobe signal, and a column-address-strobe signal; and wherein, whenever said monitor circuitry indicates that the system power supply voltage has returned to said acceptable range after having been outside of said acceptable range, said refresh control signal generation logic thereupon begins to provide a continuous series of said refresh control signals as an output to the memories.

Claim 47

A computer system, comprising: at least one input device; at least one output device; at least one processor unit; a power supply, which provides a system supply voltage on at least one system supply voltage line; at least one battery, which has an operating voltage which is higher than the highest normal value of the system power supply voltage; and at least one memory subsystem comprising: at least nine dynamic random access memories (DRAMs), having input connections to receive row-address-strobe and column-address-strobe signals, said DRAM chips being internally configured to begin a refresh cycle upon receiving a column-address-strobe-before-row-address-strobe signal sequence, said DRAMs being of a kind which does not require externally supplied row addresses for refresh; and a controller, comprising connections for refresh control signal input and output, and wherein said refresh control signal input includes at least four signal lines, including row-address-strobe and column-address-strobe signals, and wherein, when no power failure has been detected, said controller connects said refresh control signal input through to said refresh control signal output; wherein said controller is connected and programmed to connect said system supply voltage line to said power supply connections of said DRAMs under normal operating conditions; wherein said controller is also connected and programmed to receive and regulate the output of said battery, with reference to a bandgap voltage reference circuit, to thereby provide a supply voltage output to said power supply connections of said DRAMs when a power failure has been detected, said supply voltage output having a discrete capacitor connected thereto; and wherein said controller provides refresh control signals, with appropriate timing, to said DRAMs, when a power failure has been detected, if said controller has been programmed to apply refresh control signals to said DRAMs if the system power supply fails; individual ones of said memory subsystems being separately mounted on individual physically separate modules.

Claim 48

A computer system, comprising: at least one input device; at least one output device; at least one processor unit; a power supply, which provides a system supply voltage on at least one system supply voltage line; at least one battery, which has an operating voltage which is higher than the highest normal value of the system power supply voltage; and at least one memory subsystem comprising: at least nine dynamic random access memories (DRAMs), having input connections to receive row-address-strobe and column-address-strobe signals, said DRAM chips being internally configured to begin a refresh cycle upon receiving a column-address-strobe-before-row-address-strobe signal sequence, said DRAMs being of a kind which does not require externally supplied row addresses for refresh; and a controller, comprising connections for refresh control signal input and output, and wherein said refresh control signal input includes at least four signal lines, including row-address-strobe and column-address-strobe signals, and wherein, when no power failure has been detected, said controller connects said refresh control signal input through to said refresh control signal output; wherein said controller is connected and programmed to connect said system supply voltage line to said power supply connections of said DRAMs under normal operating conditions; wherein said controller is also connected and programmed to receive and regulate the output of said battery, with reference to a bandgap voltage reference circuit, to thereby provide a supply voltage output to said power supply connections of said DRAMs when a power failure has been detected, said supply voltage output having a discrete capacitor connected thereto; and wherein said controller provides refresh control signals, with appropriate timing, to said DRAMs, when a power failure has been detected, if said controller has been programmed to apply refresh control signals to said DRAMs if the system power supply fails; individual ones of said memory subsystems being separately mounted on individual physically separate modules.

Claim 49

An integrated circuit memory controller, for attachment to a plurality of dynamic random access memories, to a battery, to a system power supply, and to leads for system-generated refresh timing signals, comprising: monitor circuitry, which monitors the absolute level of said system power supply voltage with reference to a bandgap voltage reference, and generates a failure-detect signal to indicate when the system power supply voltage is no longer within an acceptable range; voltage regulator circuitry, which comprises a bandgap voltage reference circuit, and which provides a regulated voltage, derived from the battery, to the memories in place of the system supply voltage, if either of the following conditions occur; if power-fail protection has been enabled and the system power supply voltage has departed from said acceptable range, or if power-fail protection has been enabled and the system power supply voltage is within said acceptable range and a predetermined control signal, which indicates that the system will resume control of the refresh control signals, has not been received since the system power supply voltage returned to said acceptable range; refresh control signal generation logic which, if power-fail protection has been enabled and if the system power supply voltage has departed from said acceptable range, provides refresh control signals, with appropriate timing, to the memories in place of the system-generated refresh timing signals, said refresh control signals not including row addresses; and which, if power-fail protection has been enabled and the system power supply voltage is within said acceptable range and said predetermined control signal has not been received since the system power supply voltage returned to said acceptable range, provides a continuous series of said refresh control signals as an output to the memories.

Claim 50

An integrated circuit memory controller, for attachment to a plurality of dynamic random access memories, to a battery, to a system power supply, and to leads for system-generated refresh timing signals, comprising: monitor circuitry, which monitors the absolute level of said system power supply voltage with reference to a bandgap voltage reference, and generates a failure-detect signal to indicate when the system power supply voltage is no longer within an acceptable range; voltage regulator circuitry, which comprises a bandgap voltage reference circuit, and which provides a regulated voltage, derived from the battery, to the memories in place of the system supply voltage, if either of the following conditions occur; if power-fail protection has been enabled and the system power supply voltage has departed from said acceptable range, or if power-fail protection has been enabled and the system power supply voltage is within said acceptable range and a predetermined control signal, which indicates that the system will resume control of the refresh control signals, has not been received since the system power supply voltage returned to said acceptable range; refresh control signal generation logic which, if power-fail protection has been enabled and if the system power supply voltage has departed from said acceptable range, provides refresh control signals, with appropriate timing, to the memories in place of the system-generated refresh timing signals, said refresh control signals not including row addresses; and which, if power-fail protection has been enabled and the system power supply voltage is within said acceptable range and said predetermined control signal has not been received since the system power supply voltage returned to said acceptable range, provides a continuous series of said refresh control signals as an output to the memories.