MOS Battery backup controller for microcomputer random access memory

Claim 2

In a MOS microcomputer circuit, a voltage comparator coupled to a V cc conductor and to a source of standby power for generating an output signal when the V cc level drops below a predetermined voltage level of said standby power, said comparator comprising: a voltage divider including first and second MOS transistors coupled in series between the V cc conductor and ground reference, the gates of said transistors being coupled together and to the interconnection of said first and second transistors; an inverter circuit including third and fourth MOS transistors coupled in series, said third transistor being coupled to said standby source and said fourth transistor being coupled to ground reference, the gate of said third transistor being coupled to the interconnection of said third and fourth transistors and the gate of said fourth transistor being coupled to the interconnection of said first and second transistors; and a buffer circuit including fifth and sixth series MOS transistors, said fifth transistor being coupled to said standby source and said sixth transistor being coupled to ground reference, the gate of said fifth transistor being coupled to V cc and the gate of said sixth transistor being coupled to the interconnection of said third and fourth transistors, the output of said buffer circuit being at the intersection of said fifth and sixth series transistors.

Claim 3

The voltage comparator claimed in claim 1 further including a second inverter circuit including seventh and eighth series MOS transistors, said seventh transistor being coupled to said standby source and said eighth transistor coupled to said ground reference, the gate of said eighth transistor being coupled to the interconnection of said sixth and seventh transistors and the output of said second inverter circuit being at the interconnection of said seventh and eighth transistors.

Claim 4

The comparator claimed in claim 2 wherein said first, third and seventh transistors are heavy depletion load transistors.

Claim 5

MOS microcomputer system computer control circuitry for maintaining memory sustaining voltage to a static random access memory upon failure of the system to maintain a V cc level, said control circuitry comprising: (a) input means for connecting an external battery to said control circuitry; (b) a MOS voltage comparator coupled to said input means and to a V cc conductor, said comparator generating an output signal when the V cc level drops by a predetermined amount wherein said voltage comparator comprises: (i) a voltage divider including first and second MOS transistors coupled in series between the V cc conductor and ground reference, the gates of said first and second transistors being coupled together and to the interconnection of said first and second transistors; (ii) an inverter circuit including third and fourth MOS transistors coupled in series, said third transistor being coupled to said input means and said fourth transistor being coupled to ground reference, the gate of said third transistor being coupled to the interconnection of said third and fourth transistors and the gate of said fourth transistor being coupled to the interconnection of said first and second transistors; (iii) a buffer circuit including fifth and sixth series MOS transistor, said fifth transistor being coupled to said input means and said sixth transistor being coupled to ground reference, the gate of said fifth transistor being coupled to V cc and the gate of said sixth transistor being coupled to the interconnection of said third and fourth transistors, the output of said buffer circuit being at the interconnection of said fifth and sixth series transistors; and (iv) a second inverter circuit including seventh and eighth series MOS transistors, said seventh transistor coupled to said input means and said eighth transistor coupled to said ground reference, the gate of said eighth transistor being coupled to the interconnection of said sixth and seventh transistors, the interconnection between said seventh and eighth transistors providing the output of said second inverter circuit to said MOS gating circuitry; and (c) MOS gating circuitry coupled to said input means, to said v cc conductor, and to the output conductor and responsive to the output signal of said comparator for coupling said v cc conductor to said output conductor when the voltage level on said V cc conductor remains at least as high as the voltage level of said input means, and for disconnecting the coupling to said V cc conductor and coupling said input means to said output conductor upon a lowering of said V cc by a predetermined amount.

Claim 6

MOS microcomputer system computer control circuitry for maintaining memory sustaining voltage to a static random access memory upon failure of the system to maintain a V cc level, said control circuitry comprising: (a) input means for connecting an external battery to said control circuitry; (b) a MOS voltage comparator coupled to said input means and to a V cc conductor, said comparator generating an output signal when the V cc level drops by a predetermined amount wherein said voltage comparator comprises: (i) a voltage divider including first and second MOS transistors coupled in series between the V cc conductor and ground reference, the gates of said first and second transistors being coupled together and to the interconnection of said first and second transistors; (ii) an inverter circuit including third and fourth MOS transistors coupled in series, said third transistor being coupled to said input means and said fourth transistor being coupled to ground reference, the gate of said third transistor being coupled to the interconnection of said third and fourth transistors and the gate of said fourth transistor being coupled to the interconnection of said first and second transistors; (iii) a buffer circuit including fifth and sixth series MOS transistor, said fifth transistor being coupled to said input means and said sixth transistor being coupled to ground reference, the gate of said fifth transistor being coupled to V cc and the gate of said sixth transistor being coupled to the interconnection of said third and fourth transistors, the output of said buffer circuit being at the interconnection of said fifth and sixth series transistors; and (iv) a second inverter circuit including seventh and eighth series MOS transistors, said seventh transistor coupled to said input means and said eighth transistor coupled to said ground reference, the gate of said eighth transistor being coupled to the interconnection of said sixth and seventh transistors, the interconnection between said seventh and eighth transistors providing the output of said second inverter circuit to said MOS gating circuitry; and (c) MOS gating circuitry coupled to said input means, to said v cc conductor, and to the output conductor and responsive to the output signal of said comparator for coupling said v cc conductor to said output conductor when the voltage level on said V cc conductor remains at least as high as the voltage level of said input means, and for disconnecting the coupling to said V cc conductor and coupling said input means to said output conductor upon a lowering of said V cc by a predetermined amount.

Claim 7

The control circuitry claimed in claim 4 wherein said gating circuitry includes a MOS charge pump coupled to said V cc conductor and to a two-phase clock source, said charge pump generating an output voltage more positive than said V cc level for turning on MOS gates coupled between said V cc conductor and said output conductor.

Claim 8

The control circuitry claimed in claim 5 wherein said MOS gating circuitry provides a battery charging current from said V cc to said input means.

Claim 9

The control circuitry claimed in claim 6 further including switch means responsive to a signal indicative of the existence of input power, said switch means coupled between the output of said charge pump and ground reference for grounding said output upon the removal of said input power.