US4015219A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electronic circuit using field effect transistor with compensation means
Assignee: Hitachi Ltd
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Filing: 1975-11-18
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Granted: 1977-03-29
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Expires: 1995-11-18
Abstract
Abstract In order to provide compensation for changes in the ambient temperature and supply voltage for an electronic circuit, such as a pulse generator circuit made up of MOSIC structure, a field effect transistor circuit includes a high value resistor and an enhancement and depletion type MOSFET, connected in parallel. The drain electrodes of the MOSFETs are connected to the power supply through the resistor and are also connected to the gate electrode of a depletion type load MOSFET which is the load transistor for an enhancement type MOSFET. When the compensating circuit is provided in a pulse generator circuit, instability in the oscillating frequency of the pulse generator due to changes in ambient temperature and supply voltage is overcome and the difference in the oscillating periods for the various MOSICs are decreased.
Inventors
- 👤 Hiroto Kawagoe
- 👤 Kosei Nomiya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:12
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/30; H03F1/301; H03F3/00; H03F3/34; H03F3/343; H03F3/345; H03K; H03K3/00; H03K3/01; H03K3/011; H03L; H03L1/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
261 words
A pulse generator circuit comprising first, second and third insulated gate field effect transistors of the enhancement type, the drain electrode of the first transistor being connected to the gate electrode of the second transistor, the drain electrode of the second transistor being connected to the gate electrode of the third transistor, the drain electrode of the third transistor being connected to the gate electrode of the first transistor, the source electrodes of the first, second and third transistors being connected to a first voltage source; fourth, fifth and sixth insulated gate field effect transistors of the depletion type, the source electrodes of the fourth, fifth and sixth transistors being connected to the drain electrodes of the first, second and third transistors, respectively, the drain electrodes of the fourth, fifth and sixth transistors being connected to a second voltage source, the gate electrodes of the fourth, fifth and sixth transistors being connected in common; a seventh gate field effect transistor of the enhancement type, the gate electrode of which is coupled to said second voltage source; an eighth insulated gate field effect transistor of the depletion type connected in parallel to said seventh transistor, the commonly connected source electrodes being connected to said first voltage source, the commonly connected drain electrodes being connected to the commonly connected gate electrodes of said fourth, fifth and sixth transistors, the gate electrode of the eighth transistor being connected to the source electrode thereof; and a resistor connected between the commonly connected drain electrodes of said seventh and eighth transistors and said second voltage source.
Claim 2
Dependent Claim
261 words
A pulse generator circuit comprising first, second and third insulated gate field effect transistors of the enhancement type, the drain electrode of the first transistor being connected to the gate electrode of the second transistor, the drain electrode of the second transistor being connected to the gate electrode of the third transistor, the drain electrode of the third transistor being connected to the gate electrode of the first transistor, the source electrodes of the first, second and third transistors being connected to a first voltage source; fourth, fifth and sixth insulated gate field effect transistors of the depletion type, the source electrodes of the fourth, fifth and sixth transistors being connected to the drain electrodes of the first, second and third transistors, respectively, the drain electrodes of the fourth, fifth and sixth transistors being connected to a second voltage source, the gate electrodes of the fourth, fifth and sixth transistors being connected in common; a seventh gate field effect transistor of the enhancement type, the gate electrode of which is coupled to said second voltage source; an eighth insulated gate field effect transistor of the depletion type connected in parallel to said seventh transistor, the commonly connected source electrodes being connected to said first voltage source, the commonly connected drain electrodes being connected to the commonly connected gate electrodes of said fourth, fifth and sixth transistors, the gate electrode of the eighth transistor being connected to the source electrode thereof; and a resistor connected between the commonly connected drain electrodes of said seventh and eighth transistors and said second voltage source.
Claim 3
Dependent Claim
49 words
A pulse generator circuit according to claim 1, wherein said pulse generator further includes a first capacitor connected between the drain electrode of said first transistor and said first voltage source, and a second capacitor connected between the drain electrode of said second transistor and said first voltage source.
Claim 4
Dependent Claim
221 words
A pulse generator circuit comprising: first, second and third insulated gate field effect transistors, the drain electrode of the first transistor being coupled to the gate electrode of the second transistor, the drain electrode of the second transistor being coupled to the gate electrode of the third transistor, the drain electrode of the third transistor being coupled to the gate electrode of the first transistor, and the source electrodes of the first, second and third transistors being connected to a first voltage source; fourth, fifth and sixth insulated gate field effect transistors, the source electrodes of the fourth, fifth and sixth transistors being connected to the drain electrodes of the first, second and third transistors, respectively. the drain electrodes of the fourth, fifth and sixth transistors being connected to a second voltage source, and the gate electrodes of the fourth and fifth transistors being connected in common; a seventh insulated gate field effect transistor, the source electrode of the seventh transistor being connected to said first voltage source, the drain electrode of the seventh transistor being connected to the commonly connected gate electrodes of said fourth and fifth transistors, and the gate electrode of the seventh transistor being coupled to said first voltage source; and a resistor connected between the drain electrode of said seventh transistor and said second voltage source.
Claim 5
Dependent Claim
221 words
A pulse generator circuit comprising: first, second and third insulated gate field effect transistors, the drain electrode of the first transistor being coupled to the gate electrode of the second transistor, the drain electrode of the second transistor being coupled to the gate electrode of the third transistor, the drain electrode of the third transistor being coupled to the gate electrode of the first transistor, and the source electrodes of the first, second and third transistors being connected to a first voltage source; fourth, fifth and sixth insulated gate field effect transistors, the source electrodes of the fourth, fifth and sixth transistors being connected to the drain electrodes of the first, second and third transistors, respectively. the drain electrodes of the fourth, fifth and sixth transistors being connected to a second voltage source, and the gate electrodes of the fourth and fifth transistors being connected in common; a seventh insulated gate field effect transistor, the source electrode of the seventh transistor being connected to said first voltage source, the drain electrode of the seventh transistor being connected to the commonly connected gate electrodes of said fourth and fifth transistors, and the gate electrode of the seventh transistor being coupled to said first voltage source; and a resistor connected between the drain electrode of said seventh transistor and said second voltage source.
Claim 6
Dependent Claim
49 words
A pulse generator circuit according to claim 3, wherein said pulse generator further includes a first capacitor connected between the drain electrode of said first transistor and said first voltage source, and a second capacitor coupled between the drain electrode of said second transistor and said first voltage source.
Claim 7
Dependent Claim
25 words
A pulse generator circuit according to claim 3, wherein the gate of the sixth transistor is connected to the drain electrode of said seventh transistor.
Claim 8
Dependent Claim
24 words
A pulse generator circuit according to claim 3, wherein the current flow through said resistor is substantially linearly proportional to the voltage drop thereacross.
Claim 9
Dependent Claim
74 words
A pulse generator circuit according to claim 3, wherein said pulse generator further includes an eighth insulated gate field effect transistor connected in parallel with said seventh transistor, the commonly connected source electrodes being connected to said first voltage source, the commonly connected drain electrodes being connected to the commonly connected gate electrodes of said fourth and fifth transistors, and the gate electrode of the eighth transistor being connected to the source electrode thereof.
Claim 10
Dependent Claim
24 words
A pulse generator circuit according to claim 7, wherein the current flow through said resistor is substantially linearly proportional to the voltage drop thereacross.
References Cited (Backward Citations)
US3931588A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-03-28 | 1980-09-27 | 1981-03-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-03-28 | 1984-09-27 | 1985-03-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-03-28 | 1988-09-27 | 1989-03-29 | $7700.00 | Window Closed / Lapsed |