US4594565A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clock oscillator for a cardiac pacer having frequency compensation for temperature and voltage fluctuations
Assignee: Pacesetter Inc
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Filing: 1984-08-30
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Granted: 1986-06-10
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Expires: 2004-08-30
Abstract
Abstract A temperature and voltage stable clock circuit for use in implantable cardiac pacers employs CMOS devices to minimize current drain. The circuit includes a timing capacitor which is alternately charged to and discharged between two established threshold voltages during respective charge and discharge cycles, the periods of which determine the clock frequency. To render the frequency of the clock circuit independent of changes in capacitor charge and discharge currents brought about by changes in temperature, the threshold voltage is increased with temperature so that the charge and discharge cycles remain constant. To render the frequency of the clock circuit independent of changes in the power supply voltage, a Wilson current source is used to maintain a constant charge and discharge current to the timing capacitor.
Inventors
- 👤 Francisco J. Barreras
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 23:51
CPC Classifications
A; A61; A61N; A61N1/00; A61N1/18; A61N1/32; A61N1/36; A61N1/372; A61N1/37211; A61N1/37217; A61N1/37223; A61N1/37229; A61N1/02; A61N1/025; A61N1/362; H; H03; H03K; H03K3/00; H03K3/01; H03K3/011; H03K3/02; H03K3/023; H03K3/0231; H03K3/027; H03K3/03; H03K3/0307
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
223 words
A clock circuit for use in a battery operated cardiac pacer or the like, comprising: a timing capacitor; charage circuit means operable in response to an applied bistable logic control signal for applying a charge current to said timing capacitor when said control signal is of one logic state; discharge circuit means operable in response to said applied logic control signal for applying a discharge current to said timing capacitor when said control signal is of opposite logic state; at least one of said circuit means producing a current undesirably varying as a function of ambient temperature; first threshold means responsive to the voltage level across said timing capacitor for setting said logic control signal to said one logic state to inhibit said discharge circuit means and actuate said charge circuit means upon said capacitor voltage reaching a first threshold voltage; second threshold means responsive to the voltage level across said timing capacitor for setting said logic control signal to said opposite logic state to inhibit said charge circuit means and actuate said discharge circuit means upon said capacitor voltage reaching a second threshold voltage; and temperature compensating means in circuit relationship with at least one of said threshold means for varying the threshold voltage thereof in response to changes in temperature whereby the frequency remains substantially constant notwithstanding changes in ambient temperature.
Claim 2
Dependent Claim
223 words
A clock circuit for use in a battery operated cardiac pacer or the like, comprising: a timing capacitor; charage circuit means operable in response to an applied bistable logic control signal for applying a charge current to said timing capacitor when said control signal is of one logic state; discharge circuit means operable in response to said applied logic control signal for applying a discharge current to said timing capacitor when said control signal is of opposite logic state; at least one of said circuit means producing a current undesirably varying as a function of ambient temperature; first threshold means responsive to the voltage level across said timing capacitor for setting said logic control signal to said one logic state to inhibit said discharge circuit means and actuate said charge circuit means upon said capacitor voltage reaching a first threshold voltage; second threshold means responsive to the voltage level across said timing capacitor for setting said logic control signal to said opposite logic state to inhibit said charge circuit means and actuate said discharge circuit means upon said capacitor voltage reaching a second threshold voltage; and temperature compensating means in circuit relationship with at least one of said threshold means for varying the threshold voltage thereof in response to changes in temperature whereby the frequency remains substantially constant notwithstanding changes in ambient temperature.
Claim 3
Dependent Claim
20 words
A clock circuit as defined in claim 1 wherein said charge and discharge circuit means include a constant current source.
Claim 4
Dependent Claim
20 words
A clock circuit as defined in claim 2 wherein said constant current source current varies as a function of temperature.
Claim 5
Dependent Claim
40 words
A clock circuit as defined in claim 3 wherein said first threshold voltage increases in proportion to temperature induced increases in said constant current source current and decreases in proportion to temperature induced decreases in said constant current source current.
Claim 6
Dependent Claim
53 words
A clock circuit as defined in claim 1 wherein said temperature compensating means include a MOS transistor acting as a temperature-dependent active load to another MOS transistor, thereby causing the associated threshold voltage to vary directly in response to temperature induced changes in the rate of charge and discharge of the timing capacitor.
Claim 7
Dependent Claim
175 words
A clock circuit comprising: a timing capacitor for providing an increasing capacitor voltage in response to being charged by a charge current and providing a decreasing capacitor voltage in response to being discharged by a discharge current; capacitor charge circuity having a charge period during which said charge current is provided to said timing capacitor, and having a discharge period during which said discharge current is drawn from said timing capacitor, at least one of said currents being undesirably dependent on ambient temperature, said charge and discharge periods alternately occurring in response to an applied control signal; clock control circuity having lower and upper threshold voltages, and responsive to said capacitor voltage, whereby said control signal is provided and applied to said capacitor charge circuitry in response to said capacitor voltage alternately reaching said upper and lower threshold voltages; and temperature compensating circuitry for varying at least one of said threshold voltages in response to changes in ambient operating temperature to maintain a substantially constant charge-discharge cycle frequency notwithstanding changes in said ambient operating temperature.
Claim 8
Dependent Claim
175 words
A clock circuit comprising: a timing capacitor for providing an increasing capacitor voltage in response to being charged by a charge current and providing a decreasing capacitor voltage in response to being discharged by a discharge current; capacitor charge circuity having a charge period during which said charge current is provided to said timing capacitor, and having a discharge period during which said discharge current is drawn from said timing capacitor, at least one of said currents being undesirably dependent on ambient temperature, said charge and discharge periods alternately occurring in response to an applied control signal; clock control circuity having lower and upper threshold voltages, and responsive to said capacitor voltage, whereby said control signal is provided and applied to said capacitor charge circuitry in response to said capacitor voltage alternately reaching said upper and lower threshold voltages; and temperature compensating circuitry for varying at least one of said threshold voltages in response to changes in ambient operating temperature to maintain a substantially constant charge-discharge cycle frequency notwithstanding changes in said ambient operating temperature.
Claim 9
Dependent Claim
25 words
A clock circuit as defined in claim 6 wherein said capacitor charge circuit includes a constant current source for providing said charge and discharge curents.
Claim 10
Dependent Claim
23 words
A clock circuit as defined in claim 7 wherein the current supplied by said constant current source varies as a function of temperature.
Claim 11
Dependent Claim
52 words
A clock circuit as defined in claim 8 wherein said lower threshold voltage varies as a function of temperature so that said upper threshold voltage increases in proportion to temperature induced increases in said constant current source current and decreases in proportion to temperature induced decreases in said constant current source current.
Claim 12
Dependent Claim
41 words
A clock circuit as defined in claim 9 wherein said temprature compensating circuitry varies said lower threshold voltage in response to changing temperature so that said charge and discharge periods remain substantially constant over a range of said ambient operating temperatures.
Claim 13
Dependent Claim
52 words
A clock circuit as defined in claim 10 wherein said temperature compensating circuitry includes a MOS transistor acting as temperature dependent active load to another MOS transistor, thereby causing said lower threshold voltage to vary in response to temperature induced changes in the rate of charge and discharge of the timing capacitor.
Claim 14
Dependent Claim
15 words
A clock circuit as defined in claim 11 wherein all active devices comprise CMOS devices.
Claim 15
Dependent Claim
21 words
A clock circuit as defined in claim 6 wherein said timing capacitor charge current is greater than said capacitor discharge current.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-09 | 1989-12-09 | 1990-06-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-09 | 1993-12-09 | 1994-06-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-09 | 1997-12-09 | 1998-06-10 | $7700.00 | Window Closed / Lapsed |