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Patent US4972518A successfully refreshed from Google Patents.
US4972518A
Expired / Lapsed
US
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Logic integrated circuit having input and output flip-flops to stabilize pulse durations
Assignee: NEC Corp
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Filing: 1989-07-25
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Granted: 1990-11-20
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Expires: 2009-07-25
Abstract
Abstract A logic integrated circuit comprises a logic circuit, an input-stage flip-flop connected to the input of the logic circuit and an output-stage flip-flop connected to the output of the logic circuit. Each of the input- and output-stage flip-flops is responsive to a clock pulse to change their output logic states depending on their input logic states, so that an output pulse generated by each of the flip-flops has a duration which is determined exclusively by the interval between successive clock pulses.
Inventors
- 👤 Hiroyuki Matsuo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:46
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/156; H03K5/01; H03K5/04; H03K5/05
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
303 words
A data processor comprising: a clock source for generating clock pulses; first and second input-stage integrated circuits chips; third output-stage integrated circuit chip; and means for connecting an output terminal of said first input-stage integrated circuit chip to an input terminal of said third output-stage integrated circuit chip and for connecting an output terminal of said second input-stage integrated circuit chip to an input terminal of said third output-stage integrated circuit chip, at least one of said first and second integrated circuit chips comprising: a first logic circuit; an input-stage flip-flop having a logic input terminal connected to an input terminal of the chip and a logic output terminal connected to an input of said first logic circuit; and an output-stage flip-flop having a logic input terminal connected to an output of said first logic circuit and a logic output terminal, said third integrated circuit chip comprising: a selector having first and second inputs connected respectively to the logic output terminals of the output-stage flip-flops of said first and second integrated circuit chips for selectively applying signals from said first and second integrated circuit chips to an output terminal thereof; a second logic circuit; and an input-stage flip-flop having a logic input terminal connected to the output terminal of said selector and a logic output terminal connected to an input of said second logic circuit, each said input-stage flip-flop and each said output-stage flip-flop of said first and second integrated circuit chips being responsive to said clock pulses for changing logic states at their logic output terminals to the logic states of their logic input terminals, and said input-stage flip-flop of said third integrated circuit chip being responsive to said clock pulses for changing a logic state at the logic output terminal thereof to the logic state of the logic input terminal thereof.
Claim 2
Dependent Claim
303 words
A data processor comprising: a clock source for generating clock pulses; first and second input-stage integrated circuits chips; third output-stage integrated circuit chip; and means for connecting an output terminal of said first input-stage integrated circuit chip to an input terminal of said third output-stage integrated circuit chip and for connecting an output terminal of said second input-stage integrated circuit chip to an input terminal of said third output-stage integrated circuit chip, at least one of said first and second integrated circuit chips comprising: a first logic circuit; an input-stage flip-flop having a logic input terminal connected to an input terminal of the chip and a logic output terminal connected to an input of said first logic circuit; and an output-stage flip-flop having a logic input terminal connected to an output of said first logic circuit and a logic output terminal, said third integrated circuit chip comprising: a selector having first and second inputs connected respectively to the logic output terminals of the output-stage flip-flops of said first and second integrated circuit chips for selectively applying signals from said first and second integrated circuit chips to an output terminal thereof; a second logic circuit; and an input-stage flip-flop having a logic input terminal connected to the output terminal of said selector and a logic output terminal connected to an input of said second logic circuit, each said input-stage flip-flop and each said output-stage flip-flop of said first and second integrated circuit chips being responsive to said clock pulses for changing logic states at their logic output terminals to the logic states of their logic input terminals, and said input-stage flip-flop of said third integrated circuit chip being responsive to said clock pulses for changing a logic state at the logic output terminal thereof to the logic state of the logic input terminal thereof.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-11-19 | 1994-05-21 | 1994-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-11-19 | 1998-05-21 | 1998-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-11-19 | 2002-05-21 | 2002-11-20 | $7700.00 | Window Closed / Lapsed |