Abstract A multiple phase CRC (cyclic redundancy check) generator having a clock phasing circuit having an input connected to the CRC clock source and a plurality of N phase clock outputs, and a plurality of N CRC circuits each having a data input, and a phase clock input each connected to one of the clock phasing circuit phase clock outputs, and each having a cyclic redundancy check output. The clock phasing circuit preferably is formed of a sequence of divided-by-two circuits each having an input and two outputs; there being N-1 divider circuits arranged in log 2 N tiers, the divider circuits of the first tier having its input connected to the clock output and the outputs of the last tier of divider circuits each being connected to separate clock inputs of the CRC circuits.
A multiple phase cyclic redundancy check (CRC) generator comprising: a source providing a sequence of clock pulses; a data stream source; a clock phasing circuit having an input connected to said source of clock pulses and a plurality of N phased clock outputs; and a plurality of N CRC circuits each having a data input connected to said data stream source, and a phased clock input each connected to one of said clock phasing circuit phased clock outputs, and each having a cyclic redundancy check output.
Claim 2
Dependent Claim
86 words
A multiple phase cyclic redundancy check (CRC) generator comprising: a source providing a sequence of clock pulses; a data stream source; a clock phasing circuit having an input connected to said source of clock pulses and a plurality of N phased clock outputs; and a plurality of N CRC circuits each having a data input connected to said data stream source, and a phased clock input each connected to one of said clock phasing circuit phased clock outputs, and each having a cyclic redundancy check output.
Claim 3
Dependent Claim
79 words
A multiple phase CRC circuit according to claim 1 wherein said clock phasing circuit comprises a sequence of divide-by-two circuits each having an input and two outputs, there being N-1 divider circuits arranged in log 2 N tiers, the divider circuit of the first tier having its input connected to said source of clock pulses, and the outputs of the last tier of divider circuits each being connected to a different one of said CRC circuits phased clock input.
Claim 4
Dependent Claim
46 words
A multiple phase CRC circuit according to claim 1 wherein said clock phasing circuit provides N phased clock outputs each having a period of N times a CRC clock period, and each being offset in time by one CRC clock period from the preceding phase clock.