US4839604A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit with clock distribution means for supplying clock signals
Assignee: NEC Corp
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Filing: 1988-03-16
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Granted: 1989-06-13
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Expires: 2008-03-16
Abstract
Abstract An integrated circuit which includes a plurality of input storage circuits, each of which has a first input terminal, a first output terminal and a first clock terminal, and, in synchronism with a clock signal fed to the first clock terminal, stores input signals sequentially appearing at the first input terminal to sequentially produce the input signals to the first output terminal. The integrated circuit further includes a logic circuit section composed of at least one of a combinational logic circuit and a sequential logic circuit, the logic circuit section being connected to the first output terminals of the first input storage circuits for receiving the input signals. The integrated circuit further includes a plurality of output storage circuits each of which has a second input terminal, a second output terminal and a second clock terminal, and, in synchronism with a clock signal fed to the second clock terminal, stores output signals sequentially supplied from the logic circuit section to the second input terminal to sequentially produce the output signals to the second output terminal, and includes clock distribution means for generating the clock signal fed to the second clock terminal and the clock signal fed to the first clock terminal which is delayed in phase relative to the clock signal fed to the second clock terminal.
Inventors
- 👤 Toshio Tanahashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:37
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
204 words
An integrated circuit comprising: a plurality of input storage circuits, each of which has a first input terminal, a first output terminal and a first clock terminal, and, in synchronism with a clock signal fed to said first clock terminal, stores input signals sequentially appearing at said first input terminal to sequentially produce said input signals to said first output terminal; a logic circuit section composed of at least one of a combinational logic circuit and a sequential logic circuit, said logic circuit section being connected to the first output terminals of said input storage circuits for receiving said input signals; a plurality of output storage circuits, each of which has a second input terminals, a second output terminal and a second clock terminal, and, in synchronism with a clock signal fed to said second clock terminal, stores output signals sequentially supplied from said logic circuit section to said second input terminal to sequentially produce said output signals to said second output terminal; and clock distribution means for generating said clock signal fed to said second clock terminal and said clock signal fed to said first clock terminal which is delayed in phase relative to said clock signal fed to said second clock terminal.
Claim 2
Dependent Claim
204 words
An integrated circuit comprising: a plurality of input storage circuits, each of which has a first input terminal, a first output terminal and a first clock terminal, and, in synchronism with a clock signal fed to said first clock terminal, stores input signals sequentially appearing at said first input terminal to sequentially produce said input signals to said first output terminal; a logic circuit section composed of at least one of a combinational logic circuit and a sequential logic circuit, said logic circuit section being connected to the first output terminals of said input storage circuits for receiving said input signals; a plurality of output storage circuits, each of which has a second input terminals, a second output terminal and a second clock terminal, and, in synchronism with a clock signal fed to said second clock terminal, stores output signals sequentially supplied from said logic circuit section to said second input terminal to sequentially produce said output signals to said second output terminal; and clock distribution means for generating said clock signal fed to said second clock terminal and said clock signal fed to said first clock terminal which is delayed in phase relative to said clock signal fed to said second clock terminal.
Claim 3
Dependent Claim
56 words
An integrated circuit as claimed in claim 1, further comprising: a plurality of third input terminals for supplying said first input terminals with said input signals which come in from outside said integrated circuit; and a plurality of third output terminals for delivering said output signals from said output storage circuits to outside said integrated circuit.
Claim 4
Dependent Claim
47 words
An integrated circuit as claimed in claim 1, further comprising: a first combinational logic circuit connected to said first input terminals; and a plurality of third input terminals for supplying said first combinational logic circuit with said input signals which come in from outside said integrated circuit.
Claim 5
Dependent Claim
37 words
An integrated circuit as claimed in claim 1, further comprising: a combinational logic circuit connected to said second output terminals; and a plurality of third output terminals for delivering said output signals to outside said integrated circuit.
Claim 6
Dependent Claim
51 words
An integrated circuit as claimed in claim 1, wherein said logic circuit section includes said sequential logic circuit and one of said clock signal fed to said first clock terminal and said clock signal fed to said second clock terminal is fed to storage circuits included in said sequential logic circuit.
Claim 7
Dependent Claim
70 words
An integrated circuit as claimed in claim 1, wherein said logic circuit section includes said sequential logic circuit and said clock distribution means is constructed to feed to storage circuits included in said sequential logic circuit a clock signal which is delayed in phase relative to said clock signal fed to said second clock terminal and advanced in phase relative to said clock signal fed to said first clock terminal.
Claim 8
Dependent Claim
38 words
An integrated circuit as claimed in claim 3, further comprising: a second combinational logic circuit connected to said second output terminals; and a plurality of third output terminals for delivering said output signals to outside said integrated circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-12 | 1992-12-12 | 1993-06-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-12 | 1996-12-12 | 1997-06-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-12 | 2000-12-12 | 2001-06-13 | $7700.00 | Window Closed / Lapsed |