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US4972105A
Expired / Lapsed
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Programmable configurable logic memory
Assignee: National Security Agency
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Filing: 1989-09-22
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Granted: 1990-11-20
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Expires: 2009-09-22
Abstract
Abstract A reprogrammable logic array is characterized by the use of a RAM fuse to selectively control the transfer of variable from input lines to intersecting output combination lines of the array. The configuration of the combiner array is programmed by writing to all of the RAM locations that are associated with the array. If a connection is to be made, a logical "1" is written to the RAM cell for that connection and if no connection is desired, a "0" is written to the RAM cell. The array which includes a novel input interface, can be quickly and easily reprogrammed simply by writing to the appropriate RAM cells. The RAM fuses may function as standard static RAM if the device does not need to function as a combiner.
Inventors
- 👤 Dennis A. Burton
- 👤 Wendy L. Goble
- 👤 Robert D. Morelli
- 👤 Thomas B. Phelps
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:32
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17712
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
110 words
A reprogrammable logic array, comprising (a) a plurality of rows of combination lines defining the output lines of the array; (b) a plurality of columns of input lines intersecting with said rows of combination lines, each of said input lines having a different input variable; (c) means connected with each intersection of said combination and input lines for controlling the transfer of an input variable from said input line to said combination line at said intersection; (d) said control means being individually reprogrammable by a RAM fuse to selectively transfer the input variables to said combination lines, thereby to produce on each output line a desired combination of input variables.
Claim 2
Dependent Claim
110 words
A reprogrammable logic array, comprising (a) a plurality of rows of combination lines defining the output lines of the array; (b) a plurality of columns of input lines intersecting with said rows of combination lines, each of said input lines having a different input variable; (c) means connected with each intersection of said combination and input lines for controlling the transfer of an input variable from said input line to said combination line at said intersection; (d) said control means being individually reprogrammable by a RAM fuse to selectively transfer the input variables to said combination lines, thereby to produce on each output line a desired combination of input variables.
Claim 3
Dependent Claim
32 words
Apparatus as defined in claim 1, and further comprising first and second arrays of lines, the output lines of said first array being connected with the input lines of said second array.
Claim 4
Dependent Claim
31 words
Apparatus as defined in claim 2, wherein the output lines of one of said arrays comprise product line and the output lines of the other of said arrays comprise sum lines.
Claim 5
Dependent Claim
27 words
Apparatus as defined in claim 3, and further comprising switching means connected with each of said input lines for transferring said input variables to said combination lines.
Claim 6
Dependent Claim
23 words
Apparatus as defined in claim 4, wherein said switching means comprises a separate transistor connected with each RAM fuse for each combination line.
Claim 7
Dependent Claim
22 words
Apparatus as defined in claim 4, wherein said switching means comprises a single transistor connected with each of said input lines, respectively.
Claim 8
Dependent Claim
42 words
Apparatus as defined in claim 1, and further comprising inverter means connected between adjacent pairs of said input lines, respectively, said inverter means being selectively operated to control the input variables and complementary variables for each of said pairs of input lines.
Claim 9
Dependent Claim
34 words
Apparatus as defined in claim 1, wherein each RAM fuse comprises a RAM cell and a transistor which operates as a fuse and whose state is controlled by data stored in said RAM cell.
Claim 10
Dependent Claim
17 words
Apparatus as defined in claim 8, wherein each RAM cell comprises a six transistor static RAM cell.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-11-19 | 1994-05-21 | 1994-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-11-19 | 1998-05-21 | 1998-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-11-19 | 2002-05-21 | 2002-11-20 | $7700.00 | Window Closed / Lapsed |