US4894558A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power saving input buffer for use with a gate array
Assignee: NEC Corp
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Filing: 1988-10-11
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Granted: 1990-01-16
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Expires: 2008-10-11
Abstract
Abstract The present invention incorporates a control mechanism in an input buffer for a gate array so that the input buffer may be directly enabled or disabled by a control signal. Hence, no power will be wasted by the unnecessary operation of gates internal to the input buffer or subsequent stages. The method of control is to couple a common control signal to one input port of each of a plurality of two-input AND gates and couple an incoming data signal to the other input port of each of the two-input AND gates. The AND gates function as input buffers and the outputs of the AND gates are applied to the subsequent stage (e.g., a gate array). Thus, a LOW control signal disables the AND gate input buffers and subsequent stages coupled to the outputs of the AND gates, regardless of whether the incoming data signals are of a HIGH or LOW state.
Inventors
- 👤 Cecil Conkle
- 👤 Masahiko Shoji
- 👤 Noriaki Takagi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 14:12
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0016; H03K19/0175; H03K19/0185; H03K19/018557
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
99 words
A device for conserving power in a gate array circuit comprising: means for supplying a first control signal; AND gate means having a first input port and a second input port and providing a first output signal, said first control signal being applied to said first input port and a first signal being applied to said second input port, wherein said first output signal is coupled to a gate array means and follows said first signal when said first control signal represents a logical one and represents a logical zero when said first control signal represents a logical zero.
Claim 2
Independent Claim
99 words
A device for conserving power in a gate array circuit comprising: means for supplying a first control signal; AND gate means having a first input port and a second input port and providing a first output signal, said first control signal being applied to said first input port and a first signal being applied to said second input port, wherein said first output signal is coupled to a gate array means and follows said first signal when said first control signal represents a logical one and represents a logical zero when said first control signal represents a logical zero.
Claim 3
Dependent Claim
25 words
The device of claim 1 wherein said AND gate means functions as one of a plurality of identical input buffers for said gate array means.
Claim 4
Dependent Claim
16 words
The device of claim 2 wherein said AND gate means is constructed using CMOS transistor technology.
Claim 5
Dependent Claim
34 words
The device of claim 2 wherein said first control signal applied to said first input port of each of said plurality of input buffers is common to each of said plurality of input buffers.
Claim 6
Dependent Claim
60 words
The device of claim 2 wherein each of said plurality of input buffers further comprises a input port for having applied thereto a control signal for independently controlling each of said input buffers, wherein if said control signal associated with a particular input buffer is a logical zero, an output of said input buffer will automatically be a logical zero.
Claim 7
Dependent Claim
118 words
The device of claim 2 further comprising a tri-state buffer means having a input port and a control signal input port and providing a output signal coupled to said second input port of said AND gate means, said control signal input port of said tri-state buffer means being coupled to a second control signal which enables or disables said tri-state buffer means, said input port of said tri-state buffer means being coupled to a output signal of said gate array means so that said second input port of said AND gate means may be selectively used as either an input port for said first signal or an output port for said output signal of said tri-state buffer means.
Claim 8
Dependent Claim
38 words
The device of claim 6 wherein said control signal of said tri-state buffer means is determined by a second output signal of said gate array means coupled to receive said first output signal of said AND gate means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-15 | 1993-07-17 | 1994-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-15 | 1997-07-17 | 1998-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-15 | 2001-07-17 | 2002-01-16 | $7700.00 | Window Closed / Lapsed |