CMOS programmable logic array using NOR gates for clocking

Claim 2

A prechargeable NOR logic gate circuit comprising: a source of electrical power including a point of reference potential; a plurality of NOR gates having input lines; a NOR gate output line; means for providing a single phase clock signal coupled to said input lines of the NOR gates, said clock signal comprising two complementary half cycles; precharge transistor means having a first current lead connected to said power source, a second current lead connected to said output line, and a control lead responsive to said clock signal means during a first one-half cycle of said clock signal to cause conduction between said current leads of said precharge transistor means for precharging said output line to the potential of said power source; a plurality of discharge transistors coupled to said plurality of NOR gates, said discharge transistors being connected in parallel, each discharge transistor having a first current lead coupled to said output line, a second current lead coupled to said reference potential, and a control lead responsive to a TRUE value NOR input signal for causing conduction between said discharge transistor current leads to discharge said output line to the potential of said point of reference potential during the second half cycle of said clock signal; and means coupled to said NOR gates for enabling said discharge transistor control leads to be driven by signals from said input lines in response to said single phase clock signal.

Claim 3

A circuit as in claim 1, wherein said prechargeable NOR logic gate circuit comprises a first logic gate circuit which is repeated a first plurality of times to form a first logic plane, in combination with a second logic gate circuit repeated a plurality of times to form a second logic plane in which each second logic gate circuit includes: an output lead; a resistive charge transistor having a first current lead connected to said power source, a second current lead connected to the second gate output line, and a control lead responsive to said clock signal in said second half cycle to cause conduction between said resistive charge transistor current leads to provide charging current for charging said second logic gate output line towards the potential of said power source; and a plurality of discharge transistors connected in parallel each having a first current lead connected to the second gate output line, a second current lead connected to said point of reference potential, and each having a control lead responsive to receiving a TRUE value NOR input signal to cause conduction between said second logic gate discharge transistor current leads to provide discharge current to override said charging current and thereby discharge said second gate output line to said point of reference potential; the output lines from one of said planes serving as input lines to the other of said planes, whereby signals applied to said one plane at the beginning of a clock signal period are combined by said planes in a selected function to produce an output signal from the other of said planes by the end of said clock signal period.

Claim 4

A circuit as in claim 2 comprising CMOS transistors having channels of one conductivity type for the precharge transistors in said first plane and for the resisitive charge transistors in said second plane, and having channels of the opposite conductivity type for the discharge transistors in both planes.

Claim 5

A circuit as in claim 3 wherein, in both said planes, said gate discharge transistor current leads are provided by source/drain diffusion regions formed beneath, and controlled by, selected control leads.

Claim 6

A circuit as in claim 2 wherein said first plane is an AND plane in which said means to enable said discharge transistor control leads applies the inverses of signals received on said gate input lines, in response to said clock signal being in said alternate phase, and wherein said second plane is an OR plane in which each said gate output line is applied to an inverter to provide a PLA output signal.

Claim 7

A programmable logic array (PLA) structure including: a source of electrical power including a point of reference potential; a first plurality of PLA input signal lines; a second plurality of PLA output signal lines; an AND plane including a third plurality of AND logic gates each comprising an AND logic gate outputline for providing a minterm output signal; discharge transitors, connected in parallel, each having a first current lead connected to said power source, a second current lead connected to the AND gate output line, and a control lead responsive to a FALSE value signal received on a PLA input signal line to cause conduction between said current leads to discharge said AND gate output line to the potential of said power source; an OR plane including a second plurality of OR logic gates each comprising an OR logic gate output line driving a respective PLA output line; discharge transistor, connected in parallel, each having a first current lead connected to the OR gate output line, a second current lead connected to said point of reference potential and a control lead responsive to receiving a TRUE value minterm signal to cause conduction between said OR gate discharge transistor current leads to discharge said OR gate output line to the potential of said point of reference potential; and means for providing a single-phase clock signal having uninverted and inverted half cycles characterized by alternate phases, said PLA structure being characterized in that: in a first of said planes, each logic gate further comprises a precharge trasnistor having a first current lead coupled to the gate output line, a second current lead coupled to said point of reference potential, and a control lead responsive to said clock signal in one precharge phase to cause conduction between said precharge transistor current leads to precharge said gate output line to the reference potential and wherein said discharge transistors only conduct to discharge said first plane logic gate output lines during an alternate discharge phase of said clock signal; and in that in the second of said planes, each logic gate further comprises a resistive charge transistor having a first current lead connected to the gate output line, a second current lead connected to the point of reference potential, and a control lead responsive to said clock signal to cause conduction between said resistive charge transistor current leads so that charging current is provided for charging said second plane logic gate output line towards the reference potential subject to being overridden by discharging current conducted through discharging transistors in said logic gate, whereby signals applied to PLA input lines at the beginning of one half cycle in a given period of the single phase clock signal are combined by the PLA, according to a programmed function, to produce sum-of-products signals at the PLA output lines by the end of the succeeding half cycle in said given period of said clock signal.

Claim 8

A programmable logic array (PLA) structure including: a source of electrical power including a point of reference potential; a first plurality of PLA input signal lines; a second plurality of PLA output signal lines; an AND plane including a third plurality of AND logic gates each comprising an AND logic gate outputline for providing a minterm output signal; discharge transitors, connected in parallel, each having a first current lead connected to said power source, a second current lead connected to the AND gate output line, and a control lead responsive to a FALSE value signal received on a PLA input signal line to cause conduction between said current leads to discharge said AND gate output line to the potential of said power source; an OR plane including a second plurality of OR logic gates each comprising an OR logic gate output line driving a respective PLA output line; discharge transistor, connected in parallel, each having a first current lead connected to the OR gate output line, a second current lead connected to said point of reference potential and a control lead responsive to receiving a TRUE value minterm signal to cause conduction between said OR gate discharge transistor current leads to discharge said OR gate output line to the potential of said point of reference potential; and means for providing a single-phase clock signal having uninverted and inverted half cycles characterized by alternate phases, said PLA structure being characterized in that: in a first of said planes, each logic gate further comprises a precharge trasnistor having a first current lead coupled to the gate output line, a second current lead coupled to said point of reference potential, and a control lead responsive to said clock signal in one precharge phase to cause conduction between said precharge transistor current leads to precharge said gate output line to the reference potential and wherein said discharge transistors only conduct to discharge said first plane logic gate output lines during an alternate discharge phase of said clock signal; and in that in the second of said planes, each logic gate further comprises a resistive charge transistor having a first current lead connected to the gate output line, a second current lead connected to the point of reference potential, and a control lead responsive to said clock signal to cause conduction between said resistive charge transistor current leads so that charging current is provided for charging said second plane logic gate output line towards the reference potential subject to being overridden by discharging current conducted through discharging transistors in said logic gate, whereby signals applied to PLA input lines at the beginning of one half cycle in a given period of the single phase clock signal are combined by the PLA, according to a programmed function, to produce sum-of-products signals at the PLA output lines by the end of the succeeding half cycle in said given period of said clock signal.

Claim 9

A PLA structure as in claim 6 wherein the first of said planes is the AND plane and the second of said planes is the OR plane.