US4611133A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed fully precharged programmable logic array
Assignee: Motorola Solutions Inc
•
Filing: 1983-05-12
•
Granted: 1986-09-09
•
Expires: 2003-05-12
Abstract
Abstract A logic array which is small in size and low in power dissipation uses only one clock signal. The array is fully precharged by precharging a first portion and a second portion and then applying ground to the first portion while delayably applying the ground to the second portion. The address is read into the first portion during the precharging to speed up operation of the array.
Inventors
- 👤 Benjamin C. Peterson
- 👤 Yoseph L. Linde
- 👤 Yigal Brandman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:32
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17716; H03K19/1772
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
95 words
A method of percharging and obtaining data from a logic array having a first portion and a second portion, each portion having a plurality of virtual ground lines, comprising: precharging the plurality of virtual ground lines in each of the first and second portions and substantially simultaneously gating in addresses to the first portion; coupling the virtual ground lines of the first portion to ground and substantially simultaneously enabling outputs from the first portion; and coupling the virtual ground lines of the second portion to ground when the outputs from the first portion have stabliized.
Claim 2
Independent Claim
95 words
A method of percharging and obtaining data from a logic array having a first portion and a second portion, each portion having a plurality of virtual ground lines, comprising: precharging the plurality of virtual ground lines in each of the first and second portions and substantially simultaneously gating in addresses to the first portion; coupling the virtual ground lines of the first portion to ground and substantially simultaneously enabling outputs from the first portion; and coupling the virtual ground lines of the second portion to ground when the outputs from the first portion have stabliized.
Claim 3
Dependent Claim
134 words
A logic array having a first portion and a second portion, comprising: the first portion having a first plurality of virtual ground lines; the second portion having a second plurality of virtual ground lines; first means for precharging the first plurality of virtual ground lines; second means for precharging the second plurality of virtual ground lines wherein a single precharge signal enables both the first and second means; third means for coupling the first plurality of virtual ground lines to ground; fourth means for coupling the second plurality of virtual ground lines to ground wherein a single control signal enables both the third and fourth means; and delay means coupled to the fourth means and responsive to the control signal for delaying the coupling of the second plurality of virtual ground lines to ground.
Claim 4
Dependent Claim
134 words
A logic array having a first portion and a second portion, comprising: the first portion having a first plurality of virtual ground lines; the second portion having a second plurality of virtual ground lines; first means for precharging the first plurality of virtual ground lines; second means for precharging the second plurality of virtual ground lines wherein a single precharge signal enables both the first and second means; third means for coupling the first plurality of virtual ground lines to ground; fourth means for coupling the second plurality of virtual ground lines to ground wherein a single control signal enables both the third and fourth means; and delay means coupled to the fourth means and responsive to the control signal for delaying the coupling of the second plurality of virtual ground lines to ground.
Claim 5
Dependent Claim
27 words
The logic array of claim 2 wherein the delay means is a heavily loaded line and wherein the control signal is a complement of the precharge signal.
Claim 6
Dependent Claim
24 words
The logic array of claim 2 wherein the first portion performs a logical AND function and the second portion performs a logical OR function.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-09-08 | 1990-03-10 | 1990-09-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-09-08 | 1994-03-10 | 1994-09-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-09-08 | 1998-03-10 | 1998-09-09 | $7700.00 | Window Closed / Lapsed |