AND-OR logic circuit including a feedback path

Claim 2

An AND-OR logic circuit having two power supply terminals and an output signal line, comprising: a first AND circuit having a plurality of series circuits which comprise transistors of a first conductivity type coupled in series along their current conduction paths and which respectively receive input signals at their respective control electrodes; a first OR circuit having transistors of a second conductivity type which have their current conduction paths selectively connected in parallel to each other between one of said power supply terminals and said output signal line and selectively receive AND signals from said series circuits at their respective control electrodes; a second AND circuit having a plurality of series circuits which comprise transistors of the first conductivity type connected in series along their current conduction paths and which selectively receive at least two output signals from said first OR circuit at their respective control electrodes; a second OR circuit having transistors of the second conductivity type which have their current conduction paths selectively connected in parallel to each other between one of said power supply terminals and said output signal line and selectively receive AND signals from said series circuits of said second AND circuit at their respective control electrodes; a precharge circuit connected between one end of each of said series circuits of said first and second AND circuits and one of said power supply terminals; a first pull-down circuit connected between the other end of each of said series circuits of said first and second AND circuits and the other of said power supply terminals; a second pull-down circuit coupled between one end of said output signal line and other of said power supply terminals; and a control means for controlling said precharge circuit and said first pull-down circuit with a first synchronizing signal and said second pull-down circuit with a second synchronizing signal of the substantially opposite phase to said first synchronizing signal.

Claim 3

An AND-OR logic circuit according to claim 1, wherein said second AND circuit has a transistor connected in series to the transistors forming the second AND circuit, said transistor selectively receiving a signal from an external circuit.

Claim 4

An AND-OR logic circuit according to claim 1, wherein the transistors of said first and second AND circuits and the transistors of said first and second OR circuits are MOS transistors.

Claim 5

An AND-OR logic circuit according to claim 1, wherein said first pull-down circuit comprises an MOS transistor of the first conductivity type which is connected between the other of said power supply terminals and said one end of each of said series circuits, and whose conduction state is controlled by one of said synchronizing signals.

Claim 6

An AND-OR logic circuit according to claim 1, wherein said precharge circuit comprises MOS transistors of the second conductivity type, each of which is connected between one of said power supply terminals and the other end of said respective series circuits, and whose conduction states are controlled by one of said synchronizing signals.

Claim 7

An AND-OR logic circuit according to claim 1, wherein said second pull-down circuit comprises MOS transistors of the first conductivity type which are connected between the other of said power supply terminals and said output signal line and whose conduction states are controlled by the other of said synchronizing signals.

Claim 8

An AND-OR logic circuit having two power supply terminals and an output signal line, comprising: a first AND circuit having a plurality of series circuits which comprise transistors of a first conductivity type coupled in series along their current conduction paths and which respectively receive input signals at their respective control electrodes; a first OR circuit having transistors of a second conductivity type which have their current conduction paths selectively connected in parallel to each other between one of said power supply terminals and said output signal line and selectively receive AND signals from said series circuits at their respective control electrodes; a second AND circuit having a plurality of series circuits which comprise transistors of the first conductivity type connected in series along their current conduction paths and which selectively receive at least one output signal from said first OR circuit and an input signal from an external circuit at their respective control electrodes; a second OR circuit having transistors of the second conductivity type which have their current conduction paths selectively connected in parallel to each other between one of said power supply terminals and said output signal line and selectively receive AND signals from said series circuits of said second AND circuit at their respective control electrodes; a precharge circuit connected between one end of each of said series circuits of said first and second AND circuits and one of said power supply terminals; a first pull-down circuit connected between the other end of each of said series circuits of said first and second AND circuits and the other of said power supply terminals; a second pull-down circuit coupled between one end of said output signal line and the other of said power supply terminals; and a control means for controlling said precharge circuit and said first pull-down circuit with a first synchronizing signal and said second pull-down circuit with a second synchronizing signal of the substantially opposite phase to said first synchronizing signal.

Claim 9

An AND-OR logic circuit having two power supply terminals and an output signal line, comprising: a first AND circuit having a plurality of series circuits which comprise transistors of a first conductivity type coupled in series along their current conduction paths and which respectively receive input signals at their respective control electrodes; a first OR circuit having transistors of a second conductivity type which have their current conduction paths selectively connected in parallel to each other between one of said power supply terminals and said output signal line and selectively receive AND signals from said series circuits at their respective control electrodes; a second AND circuit having a plurality of series circuits which comprise transistors of the first conductivity type connected in series along their current conduction paths and which selectively receive at least one output signal from said first OR circuit and an input signal from an external circuit at their respective control electrodes; a second OR circuit having transistors of the second conductivity type which have their current conduction paths selectively connected in parallel to each other between one of said power supply terminals and said output signal line and selectively receive AND signals from said series circuits of said second AND circuit at their respective control electrodes; a precharge circuit connected between one end of each of said series circuits of said first and second AND circuits and one of said power supply terminals; a first pull-down circuit connected between the other end of each of said series circuits of said first and second AND circuits and the other of said power supply terminals; a second pull-down circuit coupled between one end of said output signal line and the other of said power supply terminals; and a control means for controlling said precharge circuit and said first pull-down circuit with a first synchronizing signal and said second pull-down circuit with a second synchronizing signal of the substantially opposite phase to said first synchronizing signal.

Claim 10

An AND-OR logic circuit according to claim 7, wherein the transistors of said first and second AND circuits and the transistors of said first and second OR circuits are MOS transistors.

Claim 11

An AND-OR logic circuit according to claim 7, wherein said first pull-down circuit comprises an MOS transistor of the first conductivity type which is connected between the other of said power supply terminals and said one end of each of said series circuits, and whose conduction state is controlled by one of said synchronizing signals.

Claim 12

An AND-OR logic circuit according to claim 7, wherein said precharge circuit comprises MOS transistors of the second conductivity type, each of which is connected between one of said power supply terminals and the other end of said respective series circuits, and whose conduction states are controlled by one of said synchronizing signals.

Claim 13

An AND-OR logic circuit according to claim 7, wherein said second pull-down circuit comprises MOS transistors of the first conductivity type which are connected between the other of said power supply terminals and said output signal line and whose conduction states are controlled by the other of said synchronizing signals.