US4291247A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multistage logic circuit arrangement
Assignee: AT&T Inc
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Filing: 1979-09-21
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Granted: 1981-09-22
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Expires: 1999-09-21
Abstract
Abstract Logic circuits, particularly of the integrated semiconductor type, are accessed at improved speeds by preventing pull-ups from occurring during the access time and by the inclusion of on-chip delay circuitry to avoid switching later stages in a manner to lose information while output nodes of earlier stages are high. All stages are activated in response to a single clock pulse edge.
Inventors
- 👤 James A. Cooper, Jr.
- 👤 Robert H. Krambeck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 02:24
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0963; H03K19/01; H03K19/017; H03K19/01728
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
152 words
An electronic circuit with at least first and second stages, each of said stages including an output node and being connected between a supply voltage and a reference voltage for applying an output signal to a next consecutive stage, a logic network comprising a plurality of first active elements responsive to input signals for selectively connecting an associated one of said nodes to said reference voltage, each of said networks being connected to said reference voltage via a second active element, a load element connected between each of said nodes and said supply voltage, clock means for applying a single signal to said circuit for switching said second elements, said circuit including an on-chip delay means for avoiding premature switching of said second active element in said next consecutive stage, said first stage having a first characteristic response time, said delay means having a second characteristic response time greater than said first.
Claim 2
Dependent Claim
152 words
An electronic circuit with at least first and second stages, each of said stages including an output node and being connected between a supply voltage and a reference voltage for applying an output signal to a next consecutive stage, a logic network comprising a plurality of first active elements responsive to input signals for selectively connecting an associated one of said nodes to said reference voltage, each of said networks being connected to said reference voltage via a second active element, a load element connected between each of said nodes and said supply voltage, clock means for applying a single signal to said circuit for switching said second elements, said circuit including an on-chip delay means for avoiding premature switching of said second active element in said next consecutive stage, said first stage having a first characteristic response time, said delay means having a second characteristic response time greater than said first.
Claim 3
Dependent Claim
32 words
An electronic circuit in accordance with claim 1 wherein said load elements are active elements and said signal means is operative to switch said load elements in opposition to said second elements.
Claim 4
Dependent Claim
47 words
An electronic circuit in accordance with claim 2 wherein said delay means is connected between said clock signal means and the second active element of one of said stages for delaying the signal applied to said second element of at least a latter one of said stages.
Claim 5
Dependent Claim
13 words
An electronic circuit in accordance with claim 1 comprising an integrated semiconductor chip.
Claim 6
Dependent Claim
36 words
An electronic circuit in accordance with claim 1 wherein said load elements and said active element comprise P-channel and N-channel devices, respectively, and the gates of said elements are connected to a source of clock pulses.
Claim 7
Dependent Claim
15 words
An electronic circuit in accordance with claim 1 wherein said load elements are passive elements.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-09-21 | 1985-03-23 | 1985-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-09-21 | 1989-03-23 | 1989-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-09-21 | 1993-03-23 | 1993-09-22 | $7700.00 | Window Closed / Lapsed |