US4183093A
Expired / Lapsed
US
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Semiconductor integrated circuit device composed of insulated gate field-effect transistor
Assignee: Hitachi Ltd
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Filing: 1978-03-31
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Granted: 1980-01-08
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Expires: 1998-03-31
Abstract
Abstract In a semiconductor integrated circuit device composed of insulated gate field-effect transistors, the improvement comprises the fact that insulated gate field-effect transistors having gate insulating films of substantially equal thicknesses are arranged on a principal surface of a semiconductor substrate in the shape of a matrix. Gate input columns of the transistors are formed of polycrystalline silicon layers, and some of the transistors are enhancement type, while others are depletion type. Further, the respective transistors are formed by the self-alignment technique which employs the polycrystalline silicon layers as a diffusion mask, and the depletion type transistors are formed by implanting impurity ions opposite in the conductivity type to the substrate into selected areas of the surface of the substrate. Thus, a read only memory in a MOS-IC chip has its occupying area reduced remarkably.
Inventors
- 👤 Hiroto Kawagoe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 08:27
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/38; H10B20/383; G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G11C17/123; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
89 words
A semiconductor integrated circuit device comprising: a semiconductor body having one conductivity type; first and second matrices each including a plurality of enhancement mode and depletion mode insulated gate field effect transistors each having a source, a drain, and a gate and being arranged in and on said body in a matrix form in which said transistors are disposed along a plurality of rows and columns and said transistors in each row are connected in series; and wherein said second matrix is connected in cascade with said first matrix.
Claim 2
Dependent Claim
89 words
A semiconductor integrated circuit device comprising: a semiconductor body having one conductivity type; first and second matrices each including a plurality of enhancement mode and depletion mode insulated gate field effect transistors each having a source, a drain, and a gate and being arranged in and on said body in a matrix form in which said transistors are disposed along a plurality of rows and columns and said transistors in each row are connected in series; and wherein said second matrix is connected in cascade with said first matrix.
Claim 3
Dependent Claim
118 words
A semiconductor integrated circuit device comprising: a semiconductor body having one conductivity type; a plurality of insulated gate field effect transistors each having a source, a drain, and a gate and being arranged in and on said body in a matrix form in which said transistors are disposed along a plurality of rows and columns and the transistors in each row are connected in series; a plurality of clock controlled insulated gate field effect transistors each source electrode of which is connected in series with the drain of the transistor connected at one end of each row; and wherein the clock controlled transistors are enhancement type and selected ones of the transistors in said matrix are depletion type.
Claim 4
Dependent Claim
118 words
A semiconductor integrated circuit device comprising: a semiconductor body having one conductivity type; a plurality of insulated gate field effect transistors each having a source, a drain, and a gate and being arranged in and on said body in a matrix form in which said transistors are disposed along a plurality of rows and columns and the transistors in each row are connected in series; a plurality of clock controlled insulated gate field effect transistors each source electrode of which is connected in series with the drain of the transistor connected at one end of each row; and wherein the clock controlled transistors are enhancement type and selected ones of the transistors in said matrix are depletion type.
Claim 5
Dependent Claim
60 words
A semiconductor integrated circuit device according to claim 2, wherein for each respective row, the source of a field effect transistor in a respective column is contiguous with the drain of a field effect transistor in an adjacent column and the gates of each transistor in a respective column of said matrix are formed of a common gate electrode layer.
Claim 6
Dependent Claim
84 words
A semiconductor integrated circuit device according to claim 3, further comprising means for applying a plurality of coded true inputs to said common gate electrode layers; and a plurality of inverter circuits for applying the complements of said coded true inputs to said common gate layers, each inverter circuit including a driving insulated gate field effect transistor operating in the enhanchement mode and a load insulated gate field effect transistor operating in the depletion mode and being connected in series with said driving transistor.
Claim 7
Dependent Claim
27 words
A semiconductor integrated circuit device according to claim 4, wherein some of said transistors in said matrix are depletion mode transistors so as to form a decoder.
Claim 8
Dependent Claim
44 words
A semiconductor integrated circuit device according to claim 5, wherein the source of the transistor connected at the other end of each row is connected to a ground terminal and the drains of the clock controlled transistors are connected to a power source terminal.
Claim 9
Dependent Claim
115 words
A semiconductor integrated circuit device according to claim 5, further comprising a read only memory matrix made up of a plurality of insulated gate field effect transistors disposed in rows and columns, the transistors in each row being connected in series, and further including a multiplicity of enhancement mode insulated gate field effect transistors the source electrode of each of which is connected in series with the drain of the transistor connected at one end of each row of said read only memory matrix, and to the gate electrode of each of which there is applied a second clock pulse, and wherein said read only memory matrix is connected in cascade with said decoder matrix.
Claim 10
Dependent Claim
53 words
A semiconductor integrated circuit device according to claim 7, wherein the source of the transistor connected at the other end of the row of each matrix is connected to a ground terminal and the drains of the transistors controlled by said first and second clock pulses are connected to a power source terminal.
Claim 11
Dependent Claim
115 words
A semiconductor integrated circuit device comprising: a semiconductor body having one conductivity type; a plurality of insulated gate field effect transistors each having a source, a drain and a gate and being arranged in and on said body in a matrix form in which said transistors are disposed along a plurality of rows and columns; and a plurality of logical circuits each including a driving insulated gate field effect transistor and a load insulated gate field effect transistor being arranged in and on said body; and wherein said load transistors and selected ones of said transistors in said matrix are depletion type and said driving transistors and other transistors in said matrix are enhancement type.
Claim 12
Dependent Claim
115 words
A semiconductor integrated circuit device comprising: a semiconductor body having one conductivity type; a plurality of insulated gate field effect transistors each having a source, a drain and a gate and being arranged in and on said body in a matrix form in which said transistors are disposed along a plurality of rows and columns; and a plurality of logical circuits each including a driving insulated gate field effect transistor and a load insulated gate field effect transistor being arranged in and on said body; and wherein said load transistors and selected ones of said transistors in said matrix are depletion type and said driving transistors and other transistors in said matrix are enhancement type.
Claim 13
Dependent Claim
47 words
A semiconductor integrated circuit device according to claim 9, wherein said load transistors of said logical circuits and said selected transistors in said matrix are simultaneously formed as depletion type transistors by ion implantation of impurities determining a conductivity type opposite to that of said semiconductor body.
Claim 14
Dependent Claim
60 words
A semiconductor integrated circuit device according to claim 10, wherein for each respective row, the source of a field effect transistor in a respective column is contiguous with the drain of a field effect transistor in an adjacent column and the gates of each transistor in a respective column of said matrix are formed of a common gate electrode layer.
Claim 15
Dependent Claim
49 words
A semiconductor integrated circuit device according to claim 11, further comprising means for applying a plurality of coded true inputs to said common gate electrode layers, wherein said logical circuits are constructed as inverter circuits for applying the complements of said coded true inputs to said common gate layers.
Claim 16
Dependent Claim
74 words
A semiconductor integrated circuit device comprising: a plurality of field effect transistors connected between an output terminal and a reference terminal such that, when said transistors conduct in response to input signals applied to the gates thereof, the conduction paths between the source and drain thereof form a series current path between said output terminal and said reference terminal, and wherein at least one of said transistors is a depletion mode field effect transistor.
Claim 17
Dependent Claim
74 words
A semiconductor integrated circuit device comprising: a plurality of field effect transistors connected between an output terminal and a reference terminal such that, when said transistors conduct in response to input signals applied to the gates thereof, the conduction paths between the source and drain thereof form a series current path between said output terminal and said reference terminal, and wherein at least one of said transistors is a depletion mode field effect transistor.
Claim 18
Dependent Claim
21 words
A semiconductor integrated circuit device according to claim 13, wherein the others of said transistors are enhancement mode field effect transistors.
Claim 19
Dependent Claim
42 words
A semiconductor integrated circuit device according to claim 14, further comprising an enhancement mode field effect transistor having a source connected to said output terminal, a drain connected to a voltage source terminal and a gate connected to a clock pulse source.
Claim 20
Dependent Claim
37 words
A semiconductor integrated circuit device according to claim 15, wherein to the gate of all of said transistors connected between said output terminal and said reference terminal, data input signals, other than clock pulse signals, are applied.
Claim 21
Dependent Claim
99 words
A semiconductor integrated circuit device comprising: a semiconductor body having one conductivity type; a plurality of insulated gate field effect transistors each having a source, a drain, and a gate and being arranged in and on said body in a matrix form in which said transistors are disposed along a plurality of rows and columns and said transistors in each row are connected in series; a plurality of clock controlled insulated gate field effect transistors each source electrode of which is connected in series with the drain of the transistor connected at one end of each row is applied.
Claim 22
Dependent Claim
99 words
A semiconductor integrated circuit device comprising: a semiconductor body having one conductivity type; a plurality of insulated gate field effect transistors each having a source, a drain, and a gate and being arranged in and on said body in a matrix form in which said transistors are disposed along a plurality of rows and columns and said transistors in each row are connected in series; a plurality of clock controlled insulated gate field effect transistors each source electrode of which is connected in series with the drain of the transistor connected at one end of each row is applied.
Claim 23
Dependent Claim
89 words
A semiconductor integrated circuit comprising: a first matrix including a plurality of enhancement mode and depletion mode insulated gate field effect transistors each having a source, a drain, and a gate and being arranged in a matrix form, in which said transistors are located along a plurality of rows and columns and said transistors in each row are connected in series; and a plurality of first gate lines corresponding to said columns of transistors, the gates of each column being connected in common to the corresponding first gate lines.
Claim 24
Dependent Claim
89 words
A semiconductor integrated circuit comprising: a first matrix including a plurality of enhancement mode and depletion mode insulated gate field effect transistors each having a source, a drain, and a gate and being arranged in a matrix form, in which said transistors are located along a plurality of rows and columns and said transistors in each row are connected in series; and a plurality of first gate lines corresponding to said columns of transistors, the gates of each column being connected in common to the corresponding first gate lines.
Claim 25
Dependent Claim
119 words
A semiconductor integrated circuit according to claim 18, further comprising a second matrix including a plurality of enhancement mode and depletion mode insulated gate field effect transistors each having a source, a drain, and a gate and being arranged in a matrix form in which said transistors are located along a plurality of rows and columns and said transistors in each column are connected in series; a plurality of second gate lines corresponding to said rows of transistors, the gates of each row being connected in common to the corresponding second gate lines; and wherein each said second gate line is connected to the drain of the transistor connected at one end of each row in said first matrix.
Claim 26
Dependent Claim
29 words
A semiconductor integrated circuig according to claim 19, wherein each said second gate line is connected to a power source terminal through a switching insulated gate field effect transistor.
Claim 27
Dependent Claim
165 words
A semiconductor integrated circuit comprising: a plurality of enhancement mode and depletion mode insulated gate field effect transistors each having a source, a drain, and a gate and being arranged in a matrix form in which said transistors are located along a plurality of rows and columns and said transistors in each row are connected in series; a plurality of input terminals corresponding to said columns of transistors, the gates of each column being connected in common to the corresponding input terminals; a plurality of output terminals in which each said output terminal is connected at one end of each row of series connected transistors; and a common reference terminal being commonly connected at the other end of each row of series connected transistors; and wherein when said transistors conduct in response to input signals applied to said input terminals, at least one of said row of series connected transistors forms a series current path between the output terminal thereof and said common reference terminal.
Claim 28
Dependent Claim
165 words
A semiconductor integrated circuit comprising: a plurality of enhancement mode and depletion mode insulated gate field effect transistors each having a source, a drain, and a gate and being arranged in a matrix form in which said transistors are located along a plurality of rows and columns and said transistors in each row are connected in series; a plurality of input terminals corresponding to said columns of transistors, the gates of each column being connected in common to the corresponding input terminals; a plurality of output terminals in which each said output terminal is connected at one end of each row of series connected transistors; and a common reference terminal being commonly connected at the other end of each row of series connected transistors; and wherein when said transistors conduct in response to input signals applied to said input terminals, at least one of said row of series connected transistors forms a series current path between the output terminal thereof and said common reference terminal.
Claim 29
Dependent Claim
53 words
A semiconductor integrated circuit according to claim 21, further comprising a plurality of enhancement mode field effect transistors, each having a source connected to each said output terminal of said row of series connected transistors, a drain connected to a common source terminal and a gate connected to a common clock pulse source.
Claim 30
Dependent Claim
24 words
A semiconductor integrated circuit according to claim 22, wherein data input signals, other than a clock pulse signal, are applied to said input terminals.
Claim 31
Dependent Claim
121 words
A semiconductor integrated circuit comprising: a plurality of insulated gate field effect transistors each having a source, a drain, and a gate and being connected in series; a logical circuit including a driving insulated gate field effect transistor and a load insulated gate field effect transistor each having a source, a drain, and a gate; and wherein one end of said series connected transistors is connected to the gate of said driving transistor, the other end of said series connected transistors is connected to a ground terminal, said load resistor and at least one of the transistors in said series connected transistors are depletion type, and said driving transistor and the other transistor of said series connected transistors are enhancement type.
Claim 32
Dependent Claim
121 words
A semiconductor integrated circuit comprising: a plurality of insulated gate field effect transistors each having a source, a drain, and a gate and being connected in series; a logical circuit including a driving insulated gate field effect transistor and a load insulated gate field effect transistor each having a source, a drain, and a gate; and wherein one end of said series connected transistors is connected to the gate of said driving transistor, the other end of said series connected transistors is connected to a ground terminal, said load resistor and at least one of the transistors in said series connected transistors are depletion type, and said driving transistor and the other transistor of said series connected transistors are enhancement type.
Claim 33
Dependent Claim
47 words
A semiconductor integrated circuit according to claim 24, further comprising an enhancement type insulated gate field effect transistor having a source connected to said one end of said series connected transistors, a drain connected to a source terminal, and a gate connected to a clock pulse source.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-01-07 | 1983-07-09 | 1984-01-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-01-07 | 1987-07-09 | 1988-01-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-01-07 | 1991-07-09 | 1992-01-08 | $7700.00 | Window Closed / Lapsed |