US3866186A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic circuit arrangement employing insulated gate field effect transistors
Assignee: Toshiba Corp
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Filing: 1973-05-10
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Granted: 1975-02-11
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Expires: 1993-05-10
Abstract
Abstract A logic circuit arrangement consisting of insulated gate field effect transistors of opposite channel types wherein the drain electrode of a single first insulated gate field effect transistor of one channel type is connected to the drain electrode of at least one second insulated gate field effect transistor of the opposite channel type constituting a logic gate. The gate electrode of second transistor is supplied with a data signal and the gate electrode of first transistor and the source electrode of second transistor are supplied with clock pulse signals bearing a complementary relationship with each other. The source electrode of first transistor may receive a clock pulse signal supplied to the source electrode of second transistor or constant voltage; and an output signal from the logic circuit is delivered from the junction of the first and second transistors.
Inventors
- 👤 Yasoji Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 17:33
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0963; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17716; H03K19/1772
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
204 words
A read only memory device which comprises: a plurality of memory units each including one first insulated gate field effect transistor of one channel type having one gate electrode and a first and a second electrode forming a conduction path therebetween, and a plurality of second insulated gate field effect transistors of the opposite channel type to the first transistor each having one gate electrode and a first and a second electrode defining a conduction path therebetween, said conduction paths of said second transistors being connected in series with the conduction path of said first transistor, the second electrode of at least one of said second transistors being connected to the second electrode of said first transistor and an output from each memory unit being derived from the second electrode of said first transistor; means for supplying the gate electrodes of said second transistors of each memory unit with data signals; means for supplying the gate electrode of said first transistor of the respective memory units with a first clock pulse signal; and means for supplying the first electrode of said at least one second transistor of the respective memory units with a second clock pulse signal complementary to said first clock pulse signal.
Claim 2
Dependent Claim
204 words
A read only memory device which comprises: a plurality of memory units each including one first insulated gate field effect transistor of one channel type having one gate electrode and a first and a second electrode forming a conduction path therebetween, and a plurality of second insulated gate field effect transistors of the opposite channel type to the first transistor each having one gate electrode and a first and a second electrode defining a conduction path therebetween, said conduction paths of said second transistors being connected in series with the conduction path of said first transistor, the second electrode of at least one of said second transistors being connected to the second electrode of said first transistor and an output from each memory unit being derived from the second electrode of said first transistor; means for supplying the gate electrodes of said second transistors of each memory unit with data signals; means for supplying the gate electrode of said first transistor of the respective memory units with a first clock pulse signal; and means for supplying the first electrode of said at least one second transistor of the respective memory units with a second clock pulse signal complementary to said first clock pulse signal.
Claim 3
Dependent Claim
111 words
The read only memory device including at least two first and second read only memory devices as defined in claim 1 which are cascade connected, wherein said first transistors of said first and second read only memory devices are of the same channel type; outputs from the memory units of said first read only memory device are supplied to the gate electrodes of the second transistors of the memory units of said second read only memory device in the form of a selected combination; and said second read only memory device is supplied with clock pulse signals having a larger width than those supplied to said first read only memory device.
Claim 4
Dependent Claim
104 words
The read only memory device including at least two first and second read only memory devices as claimed in claim 1 which are cascase connected, wherein said first transistors of said first and second read only memory devices are of the same channel type; outputs from the memory units of said first read only memory device are supplied in the form of a selected combination through interposed inverter means to the gate electrodes of said second transistors of the memory units of said second read only memory device; and said first and second read only memory devices are supplied with common clock pulse signals.
Claim 5
Dependent Claim
99 words
The read only memory device including at least two first and second read only memory devices as defined in claim 1 which are cascade connected, wherein said first transistors of said first and second read only memory devices are of opposite channel types; outputs from the memory units of said first read only memory device are supplied in the form of a selected combination to the gate electrodes of said second transistors of the memory units of said second read only memory device; and said first and second read only memory devices are supplied with common clock pulse signals.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-02-10 | 1978-08-12 | 1979-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-02-10 | 1982-08-12 | 1983-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-02-10 | 1986-08-12 | 1987-02-11 | $7700.00 | Window Closed / Lapsed |