US4965219A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for the manufacturing of insulated gate field effect transistors (IGFETS) having a high response speed in high density integrated circuits
Assignee: STMicroelectronics SRL
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Filing: 1990-01-19
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Granted: 1990-10-23
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Expires: 2010-01-19
Abstract
Abstract The method involves the formation above the substrate of regions of epitaxial type automatically aligned with the gate electrode and designed to form the source and drain regions of the transistor. These regions are doped by ion implantation using a comparatively low implantation energy such that the doping agent does not penetrate into the substrate. By providing the source and drain junctions on the surface of the substrate, rather than in the substrate, there are no lateral junction capacitances and the horizontal dimensions of the IGFET may be reduced, with the result that high response speeds and high integration densities are obtained.
Inventors
- 👤 Gianfranco Cerofolini
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:42
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D30/0275; H10P; H10P14/00; H10P14/20; H10P14/24; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
118 words
A method for the formation of an insulated gate field effect transistor on a substrate of monocrystalline silicon comprising the steps of: forming a gate insulation on said substrate; forming a conductive silicon gate layer on said gate insulation; forming a screening layer over said conductive silicon gate layer; selectively etching said screening layer, said conductive silicon gate layer and said gate insulator to form exposed edges on said conductive silicon gate layer and to expose said substrate; oxidizing said exposed edges of said conductive silicon gate layer; and following said oxidizing step, depositing epitaxial silicon source-drain regions in contact with said substrate using said screening layer to avoid deposition of silicon over said conductive silicon gate layer.
Claim 2
Independent Claim
118 words
A method for the formation of an insulated gate field effect transistor on a substrate of monocrystalline silicon comprising the steps of: forming a gate insulation on said substrate; forming a conductive silicon gate layer on said gate insulation; forming a screening layer over said conductive silicon gate layer; selectively etching said screening layer, said conductive silicon gate layer and said gate insulator to form exposed edges on said conductive silicon gate layer and to expose said substrate; oxidizing said exposed edges of said conductive silicon gate layer; and following said oxidizing step, depositing epitaxial silicon source-drain regions in contact with said substrate using said screening layer to avoid deposition of silicon over said conductive silicon gate layer.
Claim 3
Dependent Claim
24 words
The method according to any one of claim 1 further including the step of doping said epitaxial source-drain regions without substantially doping said substrate.
Claim 4
Independent Claim
107 words
A method for the formation of an insulated gate field effect transistor on a substrate of monocrystalline silicon comprising the steps of, in the order recited: forming a gate insulation on said substrate; forming a conductive silicon gate layer on said gate insulation; forming a silicon nitride screening layer over said conductive silicon gate layer; selectively etching said silicon nitride screening layer, said conductive silicon gate layer and said gate insulator to form exposed edges on said conductive silicon gate layer and to expose said substrate; oxidizing said exposed edges of said conductive silicon gate layer; and growing epitaxial silicon source-drain regions in contact with said substrate.
Claim 5
Independent Claim
107 words
A method for the formation of an insulated gate field effect transistor on a substrate of monocrystalline silicon comprising the steps of, in the order recited: forming a gate insulation on said substrate; forming a conductive silicon gate layer on said gate insulation; forming a silicon nitride screening layer over said conductive silicon gate layer; selectively etching said silicon nitride screening layer, said conductive silicon gate layer and said gate insulator to form exposed edges on said conductive silicon gate layer and to expose said substrate; oxidizing said exposed edges of said conductive silicon gate layer; and growing epitaxial silicon source-drain regions in contact with said substrate.
Claim 6
Dependent Claim
12 words
The method of claim 3, wherein said screening layer comprises silicon nitride.
Claim 7
Dependent Claim
51 words
The method according to either one of claim 1, further including the step of forming a thick insulator over said substrate away from said conductive silicon gate layer, and said step of forming epitaxial silicon source-drain region in contact with said substrate includes forming a silicon layer over said thick insulator.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-22 | 1994-04-23 | 1994-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-22 | 1998-04-23 | 1998-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-22 | 2002-04-23 | 2002-10-23 | $7700.00 | Window Closed / Lapsed |