Dense EPROM having serially coupled floating gate transistors

Claim 1

A method of operating an electrically programmable memory array including a step of inhibiting the electrical WRITE operation of non-selected columns of series coupled memory cells , each of said columns having a pair of end memory cells and at least one intermediate cell, each of said memory cells including only a single transistor having spaced source and drain regions, a channel region therebetween, and only two gates, said gates respectively being a floating gate overlying and insulated from said channel region, and a control gate overlying and insulated from said floating gate, source and drain regions of said at least one intermediate cell being serially coupled only to drain and source regions, respectively, of other transistor memory cells in a corresponding column at associated intermediate connection points, each of said columns also having an isolation transistor having a source and drain coupled between one of said end cells and a first reference voltage, and a gate; a plurality of bit lines respectively coupled to said columns; said inhibiting step comprising: isolating source and drain regions of each of said columns of series coupled memory cells from said first reference voltage in response to a selected voltage applied to the gate of the isolation transistor in each of said columns; thereafter charging source and drain regions of each of said columns of series coupled memory cells to a second reference voltage with respect to a substrate in response to selected voltages applied to respective bit lines and control gates of memory cells in each of said columns of memory cells; and thereafter discharging to said first reference voltage each of the source and drain regions in a selected column of series coupled memory cells in response to selected voltages respectively applied to the bit line of said selected column and control gates of memory cells in said selected column.

Claim 2

A method of operating an electrically programmable memory array including a step of inhibiting the electrical WRITE operation of non-selected columns of series coupled memory cells , each of said columns having a pair of end memory cells and at least one intermediate cell, each of said memory cells including only a single transistor having spaced source and drain regions, a channel region therebetween, and only two gates, said gates respectively being a floating gate overlying and insulated from said channel region, and a control gate overlying and insulated from said floating gate, source and drain regions of said at least one intermediate cell being serially coupled only to drain and source regions, respectively, of other transistor memory cells in a corresponding column at associated intermediate connection points, each of said columns also having an isolation transistor having a source and drain coupled between one of said end cells and a first reference voltage, and a gate; a plurality of bit lines respectively coupled to said columns; said inhibiting step comprising: isolating source and drain regions of each of said columns of series coupled memory cells from said first reference voltage in response to a selected voltage applied to the gate of the isolation transistor in each of said columns; thereafter charging source and drain regions of each of said columns of series coupled memory cells to a second reference voltage with respect to a substrate in response to selected voltages applied to respective bit lines and control gates of memory cells in each of said columns of memory cells; and thereafter discharging to said first reference voltage each of the source and drain regions in a selected column of series coupled memory cells in response to selected voltages respectively applied to the bit line of said selected column and control gates of memory cells in said selected column.