Patent US4916338A successfully refreshed from Google Patents.
US4916338A
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US
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FET buffer amplifier
Assignee: Tektronix Inc
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Filing: 1988-12-12
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Granted: 1990-04-10
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Expires: 2008-12-12
Abstract
Abstract An FET buffer amplifier circuit includes two matched FET amplifiers each consisting of an FET transistor source follower biased by a source impedance. One FET transistor source follower receives an input voltage and the second FET transistor source follower is driven by the output of an operational amplifier. The positive and negative inputs of the operational amplifier are respectively coupled to the outputs of each FET transistor source follower. A negative feedback loop is created in which the output voltage of the operational amplifier is equal to the input voltage. The two FET transistors and source impedances are matched and are under substantially identical operating conditions.
Inventors
- 👤 Arthur J. Metz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:39
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/50; H03F3/505; H03F3/45; H03F3/45071; H03F3/45076; H03F3/4508; H03F3/45085; H03K; H03K5/00; H03K5/01; H03K5/02; H03K5/023; H03F2203/00; H03F2203/45; H03F2203/45592; H03F2203/45594
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
110 words
An FET buffer amplifier circuit having a voltage input and a voltage output comprising: (a) a first source follower FET amplifier having an input and an output, the input forming the voltage input; (b) a second source follower FET amplifier having an input and an output; and (c) an operational amplifier having a positive input, a negative input, and an output, the positive input being coupled to the output of said first source follower FET amplifier, the negative input being coupled to the output of said second source follower FET amplifier, and the output coupled to the input of said second source follower FET amplifier to form the voltage output.
Claim 2
Dependent Claim
110 words
An FET buffer amplifier circuit having a voltage input and a voltage output comprising: (a) a first source follower FET amplifier having an input and an output, the input forming the voltage input; (b) a second source follower FET amplifier having an input and an output; and (c) an operational amplifier having a positive input, a negative input, and an output, the positive input being coupled to the output of said first source follower FET amplifier, the negative input being coupled to the output of said second source follower FET amplifier, and the output coupled to the input of said second source follower FET amplifier to form the voltage output.
Claim 3
Dependent Claim
77 words
An FET buffer amplifier circuit as in claim 1 wherein each of said first and second source follower FET amplifiers comprise: (a) an FET transistor having a gate forming the input, a source, and a drain coupled to a first source of supply voltage; and (b) a source impedance having one end coupled to the source of said FET transistor to form the output, and having the other end coupled to a second source of supply voltage.
Claim 4
Dependent Claim
28 words
An operational amplifier as in claim 2 wherein the W/L ratio of both FET transistors is substantially equal, and the value of each load impedance is substantially equal.
Claim 5
Dependent Claim
98 words
An FET buffer amplifier circuit as in claim 1 wherein the operational amplifier comprises: (a) first and second bipolar transistors each having a base, an emitter, and a collector, the emitters being coupled together and to (b) a first current source, the base of the first bipolar transistor forming the positive input, the base of the second bipolar transistor forming the negative input, the collector of the first bipolar transistor being coupled to a source of supply voltage, and the collector of the second bipolar transistor being coupled to (c) a second current source to form the output.
Claim 6
Dependent Claim
138 words
An FET buffer amplifier circuit as in claim 1 wherein the operational amplifier comprises: (a) first, second, and third bipolar transistors each having a base, an emitter, and a collector, the emitters of the first and second bipolar transistors being coupled together and to (b) a first current source, the base of the first bipolar transistor forming the positive input, the base of the second bipolar transistor forming the negative input, the collector of the first bipolar transistor being coupled to a first source of supply voltage, the collector of the second bipolar transistor being coupled to (c) a second current source and to the base of the third bipolar transistor, the collector of the third bipolar transistor being coupled to a second source of supply voltage, and the emitter of the third bipolar transistor forming the output.
Claim 7
Dependent Claim
20 words
An FET buffer amplifier circuit as in claim 5 further comprising a third current source coupled to the voltage output.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-09 | 1993-10-09 | 1994-04-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-09 | 1997-10-09 | 1998-04-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-09 | 2001-10-09 | 2002-04-10 | $7700.00 | Window Closed / Lapsed |