US4910576A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory cell
Assignee: STMicroelectronics Ltd Great Britain
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Filing: 1988-01-06
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Granted: 1990-03-20
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Expires: 2008-01-06
Abstract
Abstract In a semi-conductor memory cell components are formed in regions separated from each other by one or more insulation layers (40) and first and second load resistors (20,22) and gate regions (70,72) of first and second cross-coupled driver field effect transistors (16,18) are formed in a first conductive layer (64) and the word line (36) and gate regions (66,68) of first and second transfer transistors (28,30) are formed in a second conductive layer (60).
Inventors
- 👤 Richard N. Campbell
- 👤 Jonathan Edwards
- 👤 Michael K. Thompson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:56
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/15; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
173 words
A memory cell structure on a substrate of semiconductor material having first and second cross-coupled driver field effect transistors and first and second load resistors arranged in conjunction with a power supply line and a ground line to form a flip-flop, and having first and second transfer transistors arranged in conjunction with a word line and first and second data lines for accessing data with the flip-flop, the components of the memory cell structure being formed in regions separated from each other by one or more insulation layers, in which the first and second load resistors and the gate regions of the first and second cross-coupled driver field effect transistors are formed in a first conductive layer and the word line and gate regions of the first and second transfer transistors are formed in a second conductive layer, said first conductive layer being formed prior to the formation of said second conductive layer, said first conductive layer being formed of polycrystalline silicon and said second conductive layer being formed of low resistivity silicide.
Claim 2
Dependent Claim
173 words
A memory cell structure on a substrate of semiconductor material having first and second cross-coupled driver field effect transistors and first and second load resistors arranged in conjunction with a power supply line and a ground line to form a flip-flop, and having first and second transfer transistors arranged in conjunction with a word line and first and second data lines for accessing data with the flip-flop, the components of the memory cell structure being formed in regions separated from each other by one or more insulation layers, in which the first and second load resistors and the gate regions of the first and second cross-coupled driver field effect transistors are formed in a first conductive layer and the word line and gate regions of the first and second transfer transistors are formed in a second conductive layer, said first conductive layer being formed prior to the formation of said second conductive layer, said first conductive layer being formed of polycrystalline silicon and said second conductive layer being formed of low resistivity silicide.
Claim 3
Dependent Claim
173 words
A memory cell structure on a substrate of semiconductor material having first and second cross-coupled driver field effect transistors and first and second load resistors arranged in conjunction with a power supply line and a ground line to form a flip-flop, and having first and second transfer transistors arranged in conjunction with a word line and first and second data lines for accessing data with the flip-flop, the components of the memory cell structure being formed in regions separated from each other by one or more insulation layers, in which the first and second load resistors and the gate regions of the first and second cross-coupled driver field effect transistors are formed in a first conductive layer and the word line and gate regions of the first and second transfer transistors are formed in a second conductive layer, said first conductive layer being formed prior to the formation of said second conductive layer, said first conductive layer being formed of polycrystalline silicon and said second conductive layer being formed of low resistivity polycide.
Claim 4
Dependent Claim
173 words
A memory cell structure on a substrate of semiconductor material having first and second cross-coupled driver field effect transistors and first and second load resistors arranged in conjunction with a power supply line and a ground line to form a flip-flop, and having first and second transfer transistors arranged in conjunction with a word line and first and second data lines for accessing data with the flip-flop, the components of the memory cell structure being formed in regions separated from each other by one or more insulation layers, in which the first and second load resistors and the gate regions of the first and second cross-coupled driver field effect transistors are formed in a first conductive layer and the word line and gate regions of the first and second transfer transistors are formed in a second conductive layer, said first conductive layer being formed prior to the formation of said second conductive layer, said first conductive layer being formed of polycrystalline silicon and said second conductive layer being formed of low resistivity polycide.
Claim 5
Dependent Claim
156 words
A memory cell structure on a substrate of semiconductor material having first and second cross-coupled driver field effect transistors and first and second load resistors arranged in conjunction with a power supply line and a ground line to form a flip-flop, and having first and second transfer transistors arranged in conjunction with a word line and first and second data lines for accessing data with the flip-flop, the components of the memory cell structure being formed in regions separated from each other by one or more insulation layers, in which the first and second load resistors and the gate regions of the first and second cross-coupled driver field effect transistors are formed in a first conductive layer, said first conductive layer being formed prior to the formation of said second conductive layer, said first conductive layer being formed of polycrystalline silicon and said second conductive layer being formed of a high temperature melting point refractory metal.
Claim 6
Dependent Claim
156 words
A memory cell structure on a substrate of semiconductor material having first and second cross-coupled driver field effect transistors and first and second load resistors arranged in conjunction with a power supply line and a ground line to form a flip-flop, and having first and second transfer transistors arranged in conjunction with a word line and first and second data lines for accessing data with the flip-flop, the components of the memory cell structure being formed in regions separated from each other by one or more insulation layers, in which the first and second load resistors and the gate regions of the first and second cross-coupled driver field effect transistors are formed in a first conductive layer, said first conductive layer being formed prior to the formation of said second conductive layer, said first conductive layer being formed of polycrystalline silicon and said second conductive layer being formed of a high temperature melting point refractory metal.
Claim 7
Dependent Claim
21 words
A memory cell according to claim 1 wherein the second conductive layer has a lower resistivity than said first conductive layer.
Claim 8
Dependent Claim
21 words
A memory cell according to claim 1 wherein no electrical interconnections are provided within the cell between the two conductive layers.
Claim 9
Dependent Claim
19 words
A memory cell according to claim 1 wherein said first and second conductive layers do not overlie each other.
Claim 10
Dependent Claim
16 words
A memory cell according to claim 1 wherein said memory cell comprises a static RAM cell.
Claim 11
Dependent Claim
15 words
A memory cell according to claim 1 wherein said cell is fabricated with MOS technology.
Claim 12
Dependent Claim
19 words
A memory cell according to claim 1 wherein said memory cell is formed on a substrate including CMOS circuitry.
Claim 13
Dependent Claim
14 words
A memory cell according to claim 1 wherein said memory cell includes N-channel transistors.
Claim 14
Dependent Claim
14 words
A memory cell according to claim 1 wherein said memory cell comprises P-channel transistors.
Claim 15
Dependent Claim
35 words
A memory cell according to claim 1 wherein said first conductive layer provides a direct electrical interconnection between said first and second load resistors and the gate regions of the first and second driver transistors.
Claim 16
Dependent Claim
39 words
A memory cell according to claim 1 wherein the word line and gate regions of the first and second transfer transistors are formed integrally by the second conductive layer which is of lower resistivity than the first conductive layer.
Claim 17
Dependent Claim
39 words
A memory cell according to claim 1 wherein the thickness of the insulation layer under the gate region of said driver transistors is different from the thickness of the insulation layer under the gate region of said transfer transistors.
Claim 18
Dependent Claim
24 words
A memory cell according to claim 1 wherein said driver transistors have a threshold voltage different from the threshold voltage of said transfer transistors.
Claim 19
Dependent Claim
32 words
A memory cell according to any of claims 1, 2 or 3 wherein the first conductive layer provides components which need no electrical interconnection with components provided by the second conductive layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-19 | 1993-09-18 | 1994-03-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-19 | 1997-09-18 | 1998-03-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-19 | 2001-09-18 | 2002-03-20 | $7700.00 | Window Closed / Lapsed |