US4486944A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making single poly memory cell
Assignee: Inmos Corp
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Filing: 1983-04-18
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Granted: 1984-12-11
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Expires: 2003-04-18
Abstract
Abstract A single polycrystalline silicon configuration for a memory cell in a static MOS RAM and a method of fabricating the same are described. Three conductivity regions are utilized to form each memory cell. A first conductivity region is formed in the substrate to create a buried ground line and sources and drains of transistors. A second conductivity region is formed within an insulation layer and above the first conductivity region to create a word line, gate regions of the transistors, load resistors, and a power supply line. The power supply line is oriented directly above and parallel to the ground line. A third conductivity region is formed on the surface of the insulation layer to create data lines. The number of process steps and the size of the memory cell are reduced by this configuration.
Inventors
- 👤 Kim C. Hardee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 14:28
CPC Classifications
H; H10; H10D; H10D88/00; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; H10B; H10B10/00; H10B10/15; H10W; H10W20/00; H10W20/40
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
88 words
A method for fabricating a bistable flip-flop memory cell having a pair of transfer transistors and a pair of driver transistors on a wafer of semiconductor material, including the steps of: doping to form a buried ground line beneath the surface of substrate portion of the wafer; depositing only a single layer of polycrystalline silicon ("poly") on the wafer crossing over conductive regions in the substrate; establishing insulation between the polysilicon and a metal layer to be established subsequently; and establishing metal data lines for the memory cell.
Claim 2
Independent Claim
88 words
A method for fabricating a bistable flip-flop memory cell having a pair of transfer transistors and a pair of driver transistors on a wafer of semiconductor material, including the steps of: doping to form a buried ground line beneath the surface of substrate portion of the wafer; depositing only a single layer of polycrystalline silicon ("poly") on the wafer crossing over conductive regions in the substrate; establishing insulation between the polysilicon and a metal layer to be established subsequently; and establishing metal data lines for the memory cell.
Claim 3
Dependent Claim
31 words
The method of claim 1 including delineating, in said single layer of poly, a word line and a pair of resistors separated from the substrate by a non-conductive region or layer.
Claim 4
Dependent Claim
25 words
The method of claim 1 including delineating, in said single layer of poly, a word line, a power supply line and a pair of resistors.
Claim 5
Dependent Claim
18 words
The method of claim 3 wherein said power supply line crosses over a conductive region in the substrate.
Claim 6
Dependent Claim
94 words
The method of claim 4 including: etching, prior to depositing said layer of poly, to expose first contact surfaces on the intended source and drain regions for contact with said poly; delineating the poly so that said power supply line is located above and oriented parallel to said buried ground line, and so that said poly also forms gate electrodes of the transistors; doping source and drain regions of the transistors; etching to expose second contact surfaces on the drain regions; and wherein said metal data lines are connected to said second contact surfaces.
Claim 7
Dependent Claim
16 words
The method of claim 5 wherein said buried ground line overlaps source regions of driver transistors.
Claim 8
Dependent Claim
33 words
The method of claim 5 wherein said etching step to expose first contact surfaces exposes said surfaces on the drain regions of the driver transistors and the source regions of the transfer transistors.
Claim 9
Dependent Claim
25 words
The method of claim 7 wherein said etching step to expose second contact surfaces exposes said surfaces on the drain regions of the transfer transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-12-11 | 1988-06-11 | 1988-12-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-12-11 | 1992-06-11 | 1992-12-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-12-11 | 1996-06-11 | 1996-12-11 | $7700.00 | Window Closed / Lapsed |