High density static memory cell

Claim 1

A static memory cell of the type formed in a face of a semiconductor body comprising: a pair of driver transistors each having source and drain regions, a channel, and a gate, the source and drain regions being formed by heavily doped regions in the face of the semiconductor body beneath a layer of thermal field oxide, the gate of each of the driver transistors overlying the channel thereof and being separated therefrom by a gate oxide layer much thinner than said layer of thermal field oxide; conductive means separately connected to the drain regions of each of the driver transistors and forming the gate of the other driver transistor to provide a cross-coupled bistable circuit, the conductive means at least partially overlying said layer of field oxide over said heavily doped regions; a pair of access transistors each having a source to drain path and a gate; a pair of data lines on said face with means coupling each data line separately through the source to drain path of a different one of the access transistors to the drain region of a different one of the driver transistors; an address line on said face connected to the gate of both of access transistors; and a pair of load devices at said face of the body with each load device having one electrode coupled to a voltage supply line on said face and another electrode coupled separately to a different one of said drain regions of the driver transistors.