Semiconductor device

Claim 2

A semiconductor device comprising an internal circuit having a plurality of MISFETs and an input protective circuit which has a resistor and wherein destruction of at least one of said plurality of said MISFETs in said internal circuit is prevented, said semiconductor device comprising: a semiconductor substrate having a first and a second portion, each having a first conductivity type, in order to form said input protection circuit and said internal circuit, respectively; a first semiconductor region of a second conductivity type, formed inside said first portion, said first semiconductor region including said resistor, and wherein one end portion of said first semiconductor region is connected directly to an input terminal by an aluminum layer and another end portion of said first semiconductor region is connected to a gate electrode of one of said plurality of MISFETs of said internal circuit; a second semiconductor region of a second conductivity type, formed inside said first portion, said second semiconductor region being deeper than said first semiconductor region and source and drain regions of said MISFETs in said internal circuit, and having a lower impurity concentration than the source and drain regions of said MISFETs in said internal circuit, said second semiconductor region being in contact with and disposed below said one end portion of said first semiconductor region; and a third semiconductor region of the second conductivity type, formed inside said first portion, said third semiconductor region being disposed adjacent to said second semiconductor region and separated from said second semiconductor region by a predetermined distance so that said second and third semiconductor regions at said first portion constitute a transistor for preventing the destruction of said at least one of said plurality of MISFETs.

Claim 3

A semiconductor device according to claim 1 wherein said second semiconductor region is a well region.

Claim 4

A semiconductor device according to claim 2 wherein said third semiconductor region is a well region.

Claim 5

A semiconductor device according to claim 1 wherein said third semiconductor region is a well region.

Claim 6

A semiconductor device according to claim 1 further comprising a fourth semiconductor region formed inside at a surface of said semiconductor substrate in said first portion, said fourth semiconductor region being a guard ring coupled to said third semiconductor region and extending around an outer periphery of said semiconductor substrate.

Claim 7

A semiconductor device according to claim 5 wherein said fourth semiconductor region is of the second conductivity type, and is integral with said third semiconductor region.

Claim 8

A semiconductor device according to claim 5 wherein said fourth semiconductor region is separated from said third semiconductor region, and said third and fourth semiconductor regions are connected to each other by wirings.

Claim 9

A semiconductor device according to claim 5 wherein said fourth semiconductor region is connected to a fixed potential.

Claim 10

A semiconductor device according to claim 1 wherein said input terminal is a bonding pad which extends over at least said semiconductor substrate between said second and third semiconductor regions.

Claim 11

A semiconductor device according to claim 1 further comprising an insulation film and a channel stopper region of the first conductivity type, said insulation film overlying the surface of said first portion between said second and third semiconductor regions, and said channel stopper region being disposed below said insulation film and having a higher impurity concentration than said first portion.

Claim 12

A semiconductor device comprising an internal circuit having a plurality of P-channel and N-channel MISFETs and an input protective circuit having a resistor and a MISFET connected to a diode form for preventing the destruction of at least a pair of said plurality of MISFETs in said internal circuit, said semiconductor device comprising: a semiconductor substrate having a first, second and third portion, said input protective circuit is formed in the first portion having a first conductivity type and said plurality of N-channel MISFETs are formed in the second portion having the first conductivity type and said plurality of P-channel MISFETs are formed in the third portion having a second conductivity type; a first semiconductor region of the second conductivity type, formed inside said first portion, said first semiconductor region including said resistor and wherein one end portion of said first semiconductor region is connected directly to an input terminal by an aluminum layer and another end portion of said first semiconductor region is connected to a source or drain region of said MISFET connected in a diode form and gate electrodes of at least a pair of said P-channel and N-channel MISFETs; a second semiconductor region of a second conductivity type, formed inside said first portion, said second semiconductor region being deeper than said first semiconductor region and source and drain regions of said N-channel MISFETs in said internal circuit, and having a lower impurity concentration than source and drain regions of said N-channel MISFETs in said internal circuit, said second semiconductor region being in contact with and disposed below said one end portion of said first semiconductor region; and a third semiconductor region of the second conductivity type, formed inside at a surface of said first portion, said third semiconductor region being disposed adjacent to said second semiconductor region and separated from said second semiconductor region by a predetermined distance so that said second and third semiconductor regions at said first portion constitute a transistor for preventing destruction of said at least a pair of said plurality of P-channel and N-channel MISFETs.

Claim 13

A semiconductor device comprising an internal circuit having a plurality of P-channel and N-channel MISFETs and an input protective circuit having a resistor and a MISFET connected to a diode form for preventing the destruction of at least a pair of said plurality of MISFETs in said internal circuit, said semiconductor device comprising: a semiconductor substrate having a first, second and third portion, said input protective circuit is formed in the first portion having a first conductivity type and said plurality of N-channel MISFETs are formed in the second portion having the first conductivity type and said plurality of P-channel MISFETs are formed in the third portion having a second conductivity type; a first semiconductor region of the second conductivity type, formed inside said first portion, said first semiconductor region including said resistor and wherein one end portion of said first semiconductor region is connected directly to an input terminal by an aluminum layer and another end portion of said first semiconductor region is connected to a source or drain region of said MISFET connected in a diode form and gate electrodes of at least a pair of said P-channel and N-channel MISFETs; a second semiconductor region of a second conductivity type, formed inside said first portion, said second semiconductor region being deeper than said first semiconductor region and source and drain regions of said N-channel MISFETs in said internal circuit, and having a lower impurity concentration than source and drain regions of said N-channel MISFETs in said internal circuit, said second semiconductor region being in contact with and disposed below said one end portion of said first semiconductor region; and a third semiconductor region of the second conductivity type, formed inside at a surface of said first portion, said third semiconductor region being disposed adjacent to said second semiconductor region and separated from said second semiconductor region by a predetermined distance so that said second and third semiconductor regions at said first portion constitute a transistor for preventing destruction of said at least a pair of said plurality of P-channel and N-channel MISFETs.

Claim 14

A semiconductor device according to claim 11 wherein the source and drain regions of said N-channel MISFETs provided for the internal circuit are of the second conductivity type and comprising a region of a high impurity concentration and a region of a lower impurity concentration.

Claim 15

A semiconductor device according to claim 12, wherein said region of a high impurity concentration is surrounded by said region of a lower impurity concentration.

Claim 16

A semiconductor device according to claim 13 wherein said N-channel MISFETs have a double diffused drain structure.

Claim 17

A semiconductor device according to claim 12 wherein said N-channel MISFETs of the internal circuit have a lightly doped drain.

Claim 18

A semiconductor device according to claim 11 wherein a junction provided for said first portion and said third semiconductor region is forwardly biased by a current occurring when elements comprising said input protective circuit undergo breakdown.

Claim 19

A semiconductor device according to claim 16 wherein said input protective circuit comprises said resistor and a MISFET connected in a diode form, and said breakdown is a surface breakdown of said MISFET in the diode form or a breakdown of said first semiconductor region provided for said resistor.

Claim 20

A semiconductor device according to claim 15, wherein each of said N-channel MISFETs provided for the internal circuit have a side wall insulation film on both sides of gate electrode and said region of a lower impurity concentration is formed by use of the gate electrode as a mask and said region of a high impurity concentration is formed by use of the gate electrode and the insulation film as a mask.

Claim 21

A semiconductor device according to claim 13 wherein said region of a high impurity concentration and said region of a lower inpurity concentration contain implanted arsenic ions and phosphorus ions, respectively.

Claim 22

A semiconductor device according to claim 18 wherein said region of a high impurity concentration and said region of a lower impurity concentration contain implanted arsenic ions and phosphorus ions, respectively.

Claim 23

A semiconductor device according to claim 17 wherein source and drain regions of said MISFET connected in diode form are of the second conductivity type and comprise a region of a high impurity concentration.

Claim 24

A semiconductor device according to claim 18 wherein source and drain regions of said MISFET connected in diode form are of the second conductivity type and comprise a region of a high impurity concentration.

Claim 25

A semiconductor device according to claim 11, wherein said P-channel MISFETS provided for an internal circuit are also formed in a fourth semiconductor region of second conductivity type and said fourth semiconductor region is simultaneously formed with said second and third semiconductor regions.

Claim 26

A semiconductor device according to claim 23, wherein said fourth semiconductor region is a well region.

Claim 27

A semiconductor device according to claim 11, wherein said second semiconductor region is a well region.

Claim 28

A semiconductor device according to claim 11, wherein said third semiconductor region is a well region.

Claim 29

A semiconductor device according to claim 11, further comprising a fourth semiconductor region formed inside said semiconductor substrate, said fourth semiconductor region being a guard ring coupled to said third semiconductor region and being disposed on a surface of said semiconductor substrate and extending around an outer periphery of said semiconductor substrate.

Claim 30

A semiconductor device according to claim 27, wherein said fourth semiconductor region is of the second conductivity type, and is integral with said third semiconductor region.

Claim 31

A semiconductor device according to claim 28, wherein said fourth semiconductor region is separated from said third semiconductor region, and said third and fourth semiconductor regions are connected to each other by wirings.

Claim 32

A semiconductor device according to claim 28 wherein said fourth semiconductor region is connected to a fixed potential.

Claim 33

A semiconductor device according to claim 11 wherein said input terminal is a bonding pad which extends over at least said semiconductor substrate between said second and third semiconductor regions.

Claim 34

A semiconductor device according to claim 15, wherein said P-channel MISFETs have a single drain structure.

Claim 35

A semiconductor device according to claim 14, wherein said P-channel MISFETs have a single drain structure.