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JPS5572081A Expired / Lapsed JP ⏱️ 0.0 years remaining

Input clamping circuit

Assignee: Fujitsu Ltd
•
Filing: 1978-11-27
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Granted: —
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Expires: 1998-11-27
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Abstract

Abstract PURPOSE:To accomplish sufficient protection of the internal circuits against excessive input level by arranging a static breakdown checking element and an input clamping transistor in a circuit in such a manner that the emitter of the transistor is connected to the input terminal and the internal circuits while the collector thereof to the power source. CONSTITUTION:A clamping circuit is provided with a bonding pad BP, an n<+>- type diffused resistances 11 and 12, a static breakdown checking element 13 composed of a horizontal npn-transistor made up of an n<+>-type diffused region and a p-type semiconductor substrate and the like. It is also provided with a ground 14, a terminal 17 connected to the internal circuits, and an input clamping transistor 18 composed of a horizontal npn transistor made up of an n<+>-type diffused region and a substrate, a power supply terminal 19 and the like. With such an arrangement, the emitter of the transistor 18 is connected to the terminal 17 through a contact section ct while the collector thereof to the terminal 19 through the contact ct. Excessive input, if any, can be clamped while s small number of carrier dhecked from injection to the substrate.

Inventors

  • 👤 Takumi Miyashita
  • 👤 Koichi Mikome
  • 👤 Joji Murakami
  • 👤 Yoshio Watabe
  • 👤 Takashi Matsui

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-02 02:12
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/711

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS5233486A Cited
JPS52127149A Cited
JPS52128081A Cited

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