Method of manufacturing a read only semiconductor memory device

Claim 1

A method of manufacturing memory cells in a semiconductor memory device comprising the steps of: preparing a semiconductor body; forming MOS transistors, all of said transistors having a gate region, a source region, a drain region, and a gate electrode in said semiconductor body, a completed channel and a field oxide film defining an element region of said semiconductor body on said semiconductor body; forming a first insulation layer to cover said MOS transistors; forming a first contact hole for each of the transistors in said first insulation layer so as to extend to the drain region of each said MOS transistors; forming a polycrystalline silicon layer for each of the transistors over said MOS transistors except over at least a portion of the gate region of said MOS transistors, said silicon layer extending over said field oxide film, but not over the adjacent transistors, and into the first contact hole, and directly contacting the drain region of said MOS transistors; forming a second insulation layer on at least said polycrystalline silicon layer; forming a second contact hole in said second insulation film, said second contact hole being formed on a portion of said polycrystalline silicon layer over said field oxide film; forming a metal wire layer over said MOS transistors except over at least a part of said gate region of said MOS transistors and connected to said polycrystalline silicon layer via said second contact hole to transmit output signals of said MOS transistors; and implanting ions into the gate region of said MOS transistors through said gate electrode to vary the threshold voltage after said metal wire layer is formed, thereby to write data in said MOS transistors.

Claim 2

A method of manufacturing memory cells in a semiconductor memory device comprising the steps of: preparing a semiconductor body; forming MOS transistors, all of said transistors having a gate region, a source region, a drain region, and a gate electrode in said semiconductor body, a completed channel and a field oxide film defining an element region of said semiconductor body on said semiconductor body; forming a first insulation layer to cover said MOS transistors; forming a first contact hole for each of the transistors in said first insulation layer so as to extend to the drain region of each said MOS transistors; forming a polycrystalline silicon layer for each of the transistors over said MOS transistors except over at least a portion of the gate region of said MOS transistors, said silicon layer extending over said field oxide film, but not over the adjacent transistors, and into the first contact hole, and directly contacting the drain region of said MOS transistors; forming a second insulation layer on at least said polycrystalline silicon layer; forming a second contact hole in said second insulation film, said second contact hole being formed on a portion of said polycrystalline silicon layer over said field oxide film; forming a metal wire layer over said MOS transistors except over at least a part of said gate region of said MOS transistors and connected to said polycrystalline silicon layer via said second contact hole to transmit output signals of said MOS transistors; and implanting ions into the gate region of said MOS transistors through said gate electrode to vary the threshold voltage after said metal wire layer is formed, thereby to write data in said MOS transistors.

Claim 6

A method of manufacturing a memory cell comprising the steps of: preparing a semiconductor body; forming a field oxide film above said semiconductor body; forming a gate oxide film on the semiconductor body; forming a gate electrode on the gate oxide film; forming source and drain regions in the semiconductor body by implanting ions into the semiconductor body using the gate electrode as a mask, thereby forming a MOS transistor with a completed channel; forming a first insulation layer on said MOS transistor; forming a first contact hole in said first insulation layer so as to extend to the drain region of said MOS transistor; forming a polycrystalline silicon layer over said MOS transistor except over at least a portion of the gate region of said MOS transistor, said silicon layer extending over said field oxide film, but not beyond the field oxide film and into the first contact hole, and directly contacting the drain region of said MOS transistor; forming a second insulating layer on said polycrystalline silicon layer so as to cover at least said polycrystalline silicon layer; forming a second contact hole in said second insulation film, said second contact hole being formed on a portion of said polycrystalline silicon layer over said field oxide film; forming a metal wire layer over said MOS transistor except over at least a part of said gate region of said MOS transistor and connected to said polycrystalline silicon layer via said second contact hole to transmit output signals of said MOS transistor; and implanting ions into the gate region of said MOS transistors, through said gate electrode, wherein said metal wire layer does not interfere with the flow of the ions into the gate region, to vary the threshold voltage of such MOS transistor, thereby to write data into said MOS transistor.

Claim 7

A method of manufacturing a memory cell comprising the steps of: preparing a semiconductor body; forming a field oxide film above said semiconductor body; forming a gate oxide film on the semiconductor body; forming a gate electrode on the gate oxide film; forming source and drain regions in the semiconductor body by implanting ions into the semiconductor body using the gate electrode as a mask, thereby forming a MOS transistor with a completed channel; forming a first insulation layer on said MOS transistor; forming a first contact hole in said first insulation layer so as to extend to the drain region of said MOS transistor; forming a polycrystalline silicon layer over said MOS transistor except over at least a portion of the gate region of said MOS transistor, said silicon layer extending over said field oxide film, but not beyond the field oxide film and into the first contact hole, and directly contacting the drain region of said MOS transistor; forming a second insulating layer on said polycrystalline silicon layer so as to cover at least said polycrystalline silicon layer; forming a second contact hole in said second insulation film, said second contact hole being formed on a portion of said polycrystalline silicon layer over said field oxide film; forming a metal wire layer over said MOS transistor except over at least a part of said gate region of said MOS transistor and connected to said polycrystalline silicon layer via said second contact hole to transmit output signals of said MOS transistor; and implanting ions into the gate region of said MOS transistors, through said gate electrode, wherein said metal wire layer does not interfere with the flow of the ions into the gate region, to vary the threshold voltage of such MOS transistor, thereby to write data into said MOS transistor.

Claim 9

A method of manufacturing a semiconductor memory device comprising: preparing a semiconductor body; forming a MOS transistor having a field oxide film, a gate oxide film, a gate electrode and source and drain regions in the semiconductor body; forming a first insulation layer on said MOS transistor; forming a first contact hole in said first insulation layer so as to extend to the drain region of said MOS transistor; forming a polycrystalline silicon layer over said MOS transistor except over at least a portion of the gate region of said MOS transistor, said silicon layer extending over said field oxide film, but not beyond the field oxide film, and into the first contact hole, and directly contacting the drain region of said MOS transistor; forming a second insulation layer on said polycrystalline silicon layer so as to cover at least said polycrystalline silicon layer; forming a second contact hole in said second insulation film, said second contact hole being formed on a portion of said polycrystalline silicon layer over said field oxide film; forming a metal wire layer over said MOS transistor except over at least a part of said gate region of said MOS transistor and connected to said polycrystalline silicon layer via said second contact hole to transmit output signals of said MOS transistor; and implanting ions into the gate region of said MOS transistors after said metal wire layer is formed, to vary the threshold voltage, thereby to write data into said MOS transistor.

Claim 10

A method of manufacturing a semiconductor memory device comprising: preparing a semiconductor body; forming a MOS transistor having a field oxide film, a gate oxide film, a gate electrode and source and drain regions in the semiconductor body; forming a first insulation layer on said MOS transistor; forming a first contact hole in said first insulation layer so as to extend to the drain region of said MOS transistor; forming a polycrystalline silicon layer over said MOS transistor except over at least a portion of the gate region of said MOS transistor, said silicon layer extending over said field oxide film, but not beyond the field oxide film, and into the first contact hole, and directly contacting the drain region of said MOS transistor; forming a second insulation layer on said polycrystalline silicon layer so as to cover at least said polycrystalline silicon layer; forming a second contact hole in said second insulation film, said second contact hole being formed on a portion of said polycrystalline silicon layer over said field oxide film; forming a metal wire layer over said MOS transistor except over at least a part of said gate region of said MOS transistor and connected to said polycrystalline silicon layer via said second contact hole to transmit output signals of said MOS transistor; and implanting ions into the gate region of said MOS transistors after said metal wire layer is formed, to vary the threshold voltage, thereby to write data into said MOS transistor.