Insulated gate field effect transistor circuits and their method of fabrication

Claim 1

A METHOD OF FARBICATING AN INSUALTED GATE FIELD EFFECT DEVICE CIRCUIT COMPRISING THE STEPS OF: A. FORMING A SILICON NITRIDE MASK PATTERN ON THE SURFACE OF A MONPCRYSTALLINE SILICON BODY OF ONE CONDUCTIVITY TYPE; B. EXPOSING SAID MASKED BODY TO A SUITABLE IMPURITY FOR CONVERTING THE EXPOSED PORTIONS OF THE SILICON SURFACE TO THE OPPOSITE CONDUCTIVITY TYPE FOR SOURCE, DRAIN AND DOPED INTERCONNECT REGIONS; C. EXPOSING THE MASKED BODY TO AN OXIDIZING ATMOSPHERE WHEREBY THE SLICON IS SELCTIVELY OXIDIZED TO FORM A THICK OXIDE LAYER; D. REMOVING THE MASK; E. AGAIN SUBJECTING THE BODY TO OXIDIZING CONDITIONS TO FORM A THIN OXIDE FILM HAVING THE SAME PATTERN AS SAID MASK; F. SELECTIVELY FORMING OPENINGS IN THE THICK OXIDE FOR SOURCE, DRAIN AND DOPED INTERCONNECT CONNECTIONS; G. SELECTIVELY DEPOSITING A LAYER OF POLYCRYSTALLINE SILICON ON SAID BODY TO FORM A GATE ELECTRODE IN COMBINATION WITH SOURCE, DRAIN ELECTRODES AND/OR DOPED INTERCONNECTS, A SILICON INTERCONNECT CROSSING OVER AT LEAST ONE OF SAID DIFFUSED REGIONS AND BEING INSULATED THEREFROM BY SAID THICK OXIDE LAYER; H. FORMING AN INSULATING LAYER ON SAID BODY I. SELECTIVELY FORMING OPENINGS IN THE INSULATING LAYER FOR SILICON INTERCONNECT CONNECTIONS; AND J. SELECTIVELY FORMING A PLURALITY OF CONDUCCTIVE INTERCONNECTS ON SAID BODY CONNECTING AT LEAST ONE OF SAID CONDUCTIVE INTERCONNECTS TO ONE OF SAID SILICON INTERCONNECTS AND AT LEAST ONE OF SAID CONDUCTIVE INTERCONNECTS CROSSING OVER ONE OF SAID DOPED INTERCONNECTS OR SAID SILICON INTERCONNECTS AND BEING INSULATED THREFROM BY SAID INSULATING LAYER.

Claim 2

A METHOD OF FARBICATING AN INSUALTED GATE FIELD EFFECT DEVICE CIRCUIT COMPRISING THE STEPS OF: A. FORMING A SILICON NITRIDE MASK PATTERN ON THE SURFACE OF A MONPCRYSTALLINE SILICON BODY OF ONE CONDUCTIVITY TYPE; B. EXPOSING SAID MASKED BODY TO A SUITABLE IMPURITY FOR CONVERTING THE EXPOSED PORTIONS OF THE SILICON SURFACE TO THE OPPOSITE CONDUCTIVITY TYPE FOR SOURCE, DRAIN AND DOPED INTERCONNECT REGIONS; C. EXPOSING THE MASKED BODY TO AN OXIDIZING ATMOSPHERE WHEREBY THE SLICON IS SELCTIVELY OXIDIZED TO FORM A THICK OXIDE LAYER; D. REMOVING THE MASK; E. AGAIN SUBJECTING THE BODY TO OXIDIZING CONDITIONS TO FORM A THIN OXIDE FILM HAVING THE SAME PATTERN AS SAID MASK; F. SELECTIVELY FORMING OPENINGS IN THE THICK OXIDE FOR SOURCE, DRAIN AND DOPED INTERCONNECT CONNECTIONS; G. SELECTIVELY DEPOSITING A LAYER OF POLYCRYSTALLINE SILICON ON SAID BODY TO FORM A GATE ELECTRODE IN COMBINATION WITH SOURCE, DRAIN ELECTRODES AND/OR DOPED INTERCONNECTS, A SILICON INTERCONNECT CROSSING OVER AT LEAST ONE OF SAID DIFFUSED REGIONS AND BEING INSULATED THEREFROM BY SAID THICK OXIDE LAYER; H. FORMING AN INSULATING LAYER ON SAID BODY I. SELECTIVELY FORMING OPENINGS IN THE INSULATING LAYER FOR SILICON INTERCONNECT CONNECTIONS; AND J. SELECTIVELY FORMING A PLURALITY OF CONDUCCTIVE INTERCONNECTS ON SAID BODY CONNECTING AT LEAST ONE OF SAID CONDUCTIVE INTERCONNECTS TO ONE OF SAID SILICON INTERCONNECTS AND AT LEAST ONE OF SAID CONDUCTIVE INTERCONNECTS CROSSING OVER ONE OF SAID DOPED INTERCONNECTS OR SAID SILICON INTERCONNECTS AND BEING INSULATED THREFROM BY SAID INSULATING LAYER.