US3676921A
Expired / Lapsed
US
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Semiconductor device comprising an insulated gate field effect transistor and method of manufacturing the same
Assignee: US Philips Corp
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Filing: 1970-03-16
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Granted: 1972-07-18
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Expires: 1990-03-16
Abstract
Abstract Method of making an insulated gate field effect transistor is described in which the surface of a silicon semiconductor is covered in whole or in part with a layer of a masking material which masks against oxidation, such as silicon nitride. Areas of the silicon surface are exposed for the source and drain regions, leaving the oxidation mask over the future channel. When the source and drain regions have been made, as for example by diffusion, the device is subjected to oxidation, causing the growth of a thick oxide which sinks into the silicon surface where it is not masked by the oxidation mask. Among the advantages obtained are fewer precise masking steps, a flatter device surface, and reduced gate overlap of the source and drain.
Inventors
- 👤 Else Kooi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 17:21
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/256; H10P; H10P14/00; H10P14/60; H10P14/61; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0128; H10W10/10; H10W10/13; H10W74/00; H10W74/40; Y; Y10; Y10S; Y10S148/00; Y10S148/043; Y10S148/053; Y10S148/103; Y10S148/105; Y10S148/113; Y10S148/114; Y10S148/117; Y10S438/00; Y10S438/914; Y10S438/92
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
194 words
A method of manufacturing an insulated gate field effect transistor comprising providing a silicon semiconductive body portion of one-type conductivity, providing on a surface of said body portion an impurity masking layer having at least two adjacent apertures with at least the portion of said masking layer between said apertures and at least over part of its thickness being of masking material other than silicon oxide and also capable of masking the silicon against oxidation, providing by impurity introduction through said apertures spaced surface regions of the opposite type conductivity in said body portion, thereafter subjecting at least surface portions of the body portion overlying the opposite type surface regions and adjacent the oxidation masking material to an oxidation treatment causing thereon the growth of a silicon oxide that penetrates into the body portion except where masked by oxidation masking material forming a silicon mesa under said oxidation masking material, applying a gate electrode insulated by an insulating layer which is substantially thinner than the said penetrated grown oxide from and over the surface portion extending between the opposite type surface regions, and applying source and drain connections to the opposite type surface regions.
Claim 2
Dependent Claim
40 words
A method as set forth in claim 2 wherein the oxidation treatment is continued until the thickness of the grown silicon oxide is substantially greater than that of the portion of the masking layer between the opposite type surface regions.
Claim 3
Dependent Claim
19 words
A method as set forth in claim 2 wherein the gate electrode is provided on the oxidation masking material.
Claim 4
Dependent Claim
16 words
A method as set forth in claim 2 wherein silicon nitride is the oxidation masking material.
Claim 5
Dependent Claim
51 words
A method as set forth in claim 2 wherein, after the oxidation treatment, the portion of the masking layer between the opposite type surface regions is removed and replaced by an insulating layer which is thinner than the penetrated grown oxide, and the gate electrode is provided on the insulating layer.
Claim 6
Dependent Claim
67 words
A method as set forth in claim 2 wherein the body portion is provided wiTh a masking layer which between the apertures consist essentially of a silicon oxide layer on the silicon body portion with said oxidation masking material on the silicon oxide, and following the oxidation treatment the oxidation masking material is removed and the gate electrode provided in its place on the silicon oxide layer.
Claim 7
Independent Claim
185 words
A method of manufacturing an insulated gate field-effect transistor comprising providing a silicon semiconductive body portion of one-type conductivity, providing only on a surface portion of said body portion to constitute the transistor channel a layer of diffusion masking material which at least over part of its thickness is of a material other than silicon oxide and also capable of masking the underlying silicon against oxidation, subjecting the non-masked surface portions of the body portion to a first oxidation treatment causing the growth of a silicon oxide that penetrates into the body portion except where masked by the oxidation masking material, providing adjacent opposite sides of the masking layer spaced apertures in said oxide layer, diffusing impurities into the body portion through said apertures to form opposite type source and drain regions and subjecting the body to a second oxidation treatment to cause the growth of an oxide in the apertures that penetrates into the body portion, applying a gate electrode insulated from and over the surface portion to constitute the transistor channel, and applying source and drain connections to the opposite type surface regions.
Claim 8
Independent Claim
204 words
A method of manufacturing an insulated gate field-effect transistor comprising providing a silicon semiconductive body portion of one-type conductivity, providing only on a surface portion of said body portion to constitute the transistor channel and the source and drain regions a lyer of diffusion masking material which at least over part of its thickness is of a material other than silicon oxide and also capable of masking the underlying silicon against oxidation, subjecting the non-masked surface portions of the body portion to a first oxidation treatment causing the growth of a silicon oxide that penetrates into the body except where masked by the oxidation masking material, removing spaced parts of said masking layer over the source and drain regions to be made, diffusing impurities into the body portions exposed by the removed masking layer parts to form opposite type source and drain regions and subjecting exposed body portions adjacent the surface portion to constitute the transistor channel to a second oxidation treatment to cause the growth of an oxide thereat that penetrates into the body portions, applying a gate electrode insulated from and over the surface portion to constitute the transistor channel, and applying source and drain connections to the opposite type surface regions.
Claim 9
Dependent Claim
41 words
A method as set forth in claim 9 wherein the second oxidation treatment is continued until the thickness of the grown silicon oxide is substantially greater than that of the portion of the masking layer between the opposite type surface regions.
Claim 10
Dependent Claim
19 words
A method as set forth in claim 9 wherein the gate electrode is provided on the oxidation masking material.
Claim 11
Dependent Claim
16 words
A method as set forth in claim 9 wherein silicon nitride is the oxidation masking material.
Claim 12
Dependent Claim
51 words
A method as set forth in claim 9 wherein, after the second oxidation treatment, the portion of the masking layer between the opposite type surface regions is removed and replaced by an insulating layer which is thinner than the grown oxide, and the gate electrode is provided on the insulating layer.
Claim 13
Dependent Claim
67 words
A method as set forth in claim 9 wherein the body portion is provided with a masking layer which between the apertures consists essentially of a silicon oxide layer on the silicon body portion with said oxidation masking material on the oxide layer, and following the second oxidation treatment the masking material is removed and the gate electrode provided in its place on the silicon oxide layer.
Claim 14
Dependent Claim
54 words
A methoD as set forth in claim 9 wherein the various oxide layers with various thicknesses are grown to penetrate over various distances into the body portion so as to provide a substantially flat surface on top, the gate electrode and source and drain connections having portions extending over the said substantially flat surface.
Claim 15
Independent Claim
156 words
A method of manufacturing an insulated gate field-effect transistor comprising providing a silicon semiconductive body portion of one-type conductivity, providing on a surface of the body portion a layer of diffusion masking material which at least over part of its thickness is of a material other than silicon oxide and also capable of masking the underlying silicon against oxidation, providing spaced apertures in said masking layer, diffusing impurities into the body portion through said apertures to form opposite type source and drain regions, removing the masking layer except for a portion overlying the body surface between the source and drain regions, subjecting the body portion to an oxidation treatment to cause the growth of an oxide on the non-masked surface that penetrates into the body portion, applying a gate electrode insulated from and over the surface portion extending between the opposite type surface regions, and applying source and drain connections to the opposite type surface regions.
Claim 16
Independent Claim
155 words
A method of manufacturing an insulated gate field-effect transistor comprising providing a silicon semiconductive body portion of one-type conductivity, providing only on a surface portion of said body portion to constitute the transistor channel and the source and drain regions a layer of masking material which over at least part of its thickness is of a material other than silicon oxide and capable of masking the underlying silicon against oxidation, subjecting the non-masked surface portions of the body portion to an oxidation treatment causing the growth of a silicon oxide that penetrates into the body portion except where masked by the masking material, providing spaced opposite type source and drain regions in the semiconductive part not covered by said silicon oxide, applying a gate electrode insulated from and over the surface portion extending between the opposite type source and drain regions, and applying source and drain connections to the opposite type source and drain regions.
Claim 17
Dependent Claim
22 words
A method as set forth in claim 17 wherein the masking layer over at least part of its thickness comprises silicon nitride.
Claim 18
Independent Claim
180 words
A method of manufacturing an insulated gate field effect transistor comprising providing a silicon semiconductive body portion of one-type conductivity, providing on a surface of said body portion a diffusion masking layer having at least two adjacent apertures with at least the portion of said masking layer between said apertures and at least over part of its thickness being of silicon nitride and also capable of masking the underlying silicon against oxidation, providing by diffusion through said apertures spaced surface regions of the opposite type conductivity in said body portion, thereafter subjecting at least the surface portion of the body portion overlying the opposite type surface regions to an oxidation treatment causing thereon the growth of a silicon oxide that penetrates into the body portion except where masked by said oxidation masking material forming a silicon mesa under said oxidation masking material, applying a gate electrode insulated from and over the surface portion extending between the opposite type surface regions, and applying source and drain connections through holes in the said penetrated grown oxide to the opposite type surface regions.
Claim 19
Dependent Claim
40 words
A method as set forth in claim 19 wherein the oxidation treatment is continued until the thickness of the grown silicon oxide is substantially greater than that of the portion of the masking layer between the opposite type surface regions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-07-18 | 1976-01-17 | 1976-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-07-18 | 1980-01-17 | 1980-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-07-18 | 1984-01-17 | 1984-07-18 | $7700.00 | Window Closed / Lapsed |