Dual level polysilicon single transistor-capacitor memory array

Claim 1

A semiconductor memory cell comprising: a charge storage means having an insulating layer overlying a storage region of a semiconductor body and a first conductor overlying the insulating layer; an insulated gate field effect transistor coupled to the charge storage means for controlling the flow of charge to or from the charge storage means, with said transistor having localized first and second input/output semiconductor regions of a first conductivity type and separated from one another by a channel of a second conductivity type opposite to said first type, and having a second conductor which is adapted to control the flow of charge through said channel in response to a control signal; characterized in that said first and second conductors are essentially separated from one another by the second input/output region, with the first conductor forming a first capacitor plate that is coupled to a portion of a first level conductor, and the second conductor forming a gate electrode that is coupled to a portion of a second level conductor, wherein the second level conductor overlies the first level conductor and is dielectrically spaced therefrom over a portion of said body; and wherein a surface portion of said storage region is doped with an impurity of said first conductivity type to form a second capacitor plate that contacts said second input/output region.