US4884198A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single cycle processor/cache interface
Assignee: Sun Microsystems Inc
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Filing: 1986-12-18
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Granted: 1989-11-28
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Expires: 2006-12-18
Abstract
Abstract An improved interface between a processor and an external cache system, having particular application for use in high speed computer systems. A cache memory for storing frequently accessed data is coupled to a cache address register (CAR). A processor generates addresses which correspond to locations of desired data in the cache, and provides these addresses to the CAR. Upon the receipt of a clock signal, the CAR couples the address to the cache memory. The processor includes a data register for receiving accessed cache data over a data bus. Data is latched into the register upon the receipt of a clock signal. Due to inherent delays associated with digital logic comprising the processor, clock signals provided by an external clock are received by the CAR prior to their receipt by the processor's data register. This delay (a fraction of a clock cycle) provides additional time to access the cache memory before the data is expected on the data bus. The CAR is fabricated out of a technology that allows it to drive the address to the large capacitive load of the cache memory in much less time than the processor itself could drive such a load. Thus, due to this buffering capability of the CAR, the cache can be much larger than what could be supported by the processor itself. The time expended sending the address from the processor to the CAR buffer, which would otherwise not be present if the processor addressed the cache directly from an internal register, does not subtract from the processor cycle time since the processor can compute the cache address and send it to the CAR in less than the time required to access the cache.
Inventors
- 👤 Robert B. Garner
- 👤 Anant Agrawal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:54
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0877
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
222 words
A cache access system external to a processor comprising: cache memory means including a cache memory for storing data at a plurality of addresses; cache register means coupled to said cache memory means for temporarily storing an address to be applied to said cache memory on receipt of a clock signal by said cache register means; address generation means coupled to said cache register means for generating said address and providing said address to said cache register means; clock means for generating cyclical clock signals coupled to said cache register means and said dddress generation means; cache data receiving means, internal to the processor, coupled to said cache memory means and said clock means for receiving said accessed data on receipt of said clock signal; wherein said cache register means has a first inherent delay of said clock signal and said cache data receiving means has a second inherent delay of said clock signal which is longer than said first inherent delay a fraction of a clock cycle, such that said clock signal is received by said cache data receiving means after receipt of said clock signal by said cache register means; whereby said fraction of a clock cycle provides additional time for accessing said cache memory means prior to the receipt of said clock signals by said cache data receiving means.
Claim 2
Dependent Claim
222 words
A cache access system external to a processor comprising: cache memory means including a cache memory for storing data at a plurality of addresses; cache register means coupled to said cache memory means for temporarily storing an address to be applied to said cache memory on receipt of a clock signal by said cache register means; address generation means coupled to said cache register means for generating said address and providing said address to said cache register means; clock means for generating cyclical clock signals coupled to said cache register means and said dddress generation means; cache data receiving means, internal to the processor, coupled to said cache memory means and said clock means for receiving said accessed data on receipt of said clock signal; wherein said cache register means has a first inherent delay of said clock signal and said cache data receiving means has a second inherent delay of said clock signal which is longer than said first inherent delay a fraction of a clock cycle, such that said clock signal is received by said cache data receiving means after receipt of said clock signal by said cache register means; whereby said fraction of a clock cycle provides additional time for accessing said cache memory means prior to the receipt of said clock signals by said cache data receiving means.
Claim 3
Dependent Claim
34 words
The external cache access system as defined by claim 1, wherein said cache memory means, cache register means, address generation means, and cache data receiving means are comprised of digital solid state logic devices.
Claim 4
Dependent Claim
18 words
The external cache access system as defined by claim 2, wherein said cache register means comprises a register.
Claim 5
Dependent Claim
40 words
The external cache access system as defined by claim 3, wherein said address generated by said address generation means includes a high address (AH) and a low address (AL) wherein said AL address is applied to said cache register means.
Claim 6
Dependent Claim
46 words
The external cache access system as defined by claim 5, wherein said cache register means is capable of driving a larger capacitive load than said address generation means, thereby permitting a larger cache memory than if said cache memory is driven by said address generation means.
Claim 7
Dependent Claim
20 words
The external cache access system as defined by claim 5, wherein said cache data receiving means includes a data register.
Claim 8
Dependent Claim
27 words
The external cache access system as defined by claim 6, wherein said address generation means and said cache data receiving means comprise a portion of a microprocessor.
Claim 9
Dependent Claim
203 words
A cache access system, comprising: an external cache memory for storing data at a plurality of addresses; clock means for generating cyclical clock signals; a cache address register coupled to said external cache memory and said clock means for temporarily storing an address to be provided to said cache memory to access desired data, said address being applied to said external cache memory by said cache address register upon receipt of a clock signal from said clock means; processing means coupled to said clock means, said cache address register and said external cache memory, for generating said address and providing said address to said cache address register, said processing means further including receiving means for receiving data accessed in said external cache memory on receipt of said clock signal, wherein said cache address register has a first inherent delay of said clock signal and said receiving means has a second inherent delay of said clock signal which is longer than said first inherent delay by a fraction of a clock cycle such that said clock signals are received by said cache address register prior to receipt of said clock signals by said receiving means, thereby providing additional time for accessing said cache memory.
Claim 10
Dependent Claim
203 words
A cache access system, comprising: an external cache memory for storing data at a plurality of addresses; clock means for generating cyclical clock signals; a cache address register coupled to said external cache memory and said clock means for temporarily storing an address to be provided to said cache memory to access desired data, said address being applied to said external cache memory by said cache address register upon receipt of a clock signal from said clock means; processing means coupled to said clock means, said cache address register and said external cache memory, for generating said address and providing said address to said cache address register, said processing means further including receiving means for receiving data accessed in said external cache memory on receipt of said clock signal, wherein said cache address register has a first inherent delay of said clock signal and said receiving means has a second inherent delay of said clock signal which is longer than said first inherent delay by a fraction of a clock cycle such that said clock signals are received by said cache address register prior to receipt of said clock signals by said receiving means, thereby providing additional time for accessing said cache memory.
Claim 11
Dependent Claim
17 words
The cache access system as defined by claim 8, wherein said cache register means comprises a register.
Claim 12
Dependent Claim
39 words
The cache access system as defined by claim 9, wherein said address generated by said address generation means includes a high address (AH) and a low address (AL) wherein said AL address is applied to said cache register means.
Claim 13
Dependent Claim
19 words
The cache access system as defined by claim 9, wherein said cache data receiving means includes a data register.
Claim 14
Dependent Claim
45 words
The cache access system as defined by claim 11, wherein said cache address register is capable of driving a larger capacitive load then said processing means, thereby permitting a larger external cache memory than if said cache memory is driven directly by said processing means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-27 | 1993-05-29 | 1993-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-27 | 1997-05-29 | 1997-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-27 | 2001-05-29 | 2001-11-28 | $7700.00 | Window Closed / Lapsed |