Dual clocking time delay generation circuit

Claim 2

A circuit for generating two separate clocking signals having a delay period, d i , therebetween, said dual clocking delay circuit comprising: (a) first means to generate a ramp voltage; (b) second means to generate an analog voltage proportional to a time period; (c) third means to set an initial voltage representing a time (T 0 ) which will initiate a first output clock signal when said ramp voltage is equal to said initial voltage; (d) fourth means to provide a first output clock signal at said time (T 0 ); (e) fifth means to initiate a second output clock signal at a time (T 1 ) upon sensing voltage equality between said ramp voltage and said time period analog voltage; (f) reference clock means to energize said first and second means.

Claim 3

The dual clock delay circuit of claim 1, wherein the delay period, d i , between said first and second clock output signals is controlled by said means to set an initial voltage.

Claim 4

The dual clock delay circuit of claim 1, wherein said delay period (d i ) is controlled by the slope of said ramp voltage.

Claim 5

The dual clock delay circuit of claim 1, wherein the said delay period (d i ) is controlled by both the voltage setting of said initial voltage and the setting of the slope of said ramp voltage.

Claim 6

The circuit of claim 1, wherein said first means includes: (5i) an adjustable constant current source connected to a capacitor bank and an output ramp voltage line; (5ii) a capacitor bank energized and clocked by said reference clock; (5iii) an output ramp voltage line.

Claim 7

The circuit of claim 1, wherein said second means includes: (6i) a digital analog converter for converting digital time period signals to a proportional analog voltage; (6ii) means, clocked by said reference clock, to generate digital time period signals and connected to said fourth means.

Claim 8

The circuit of claim 6, wherein said means to generate digital time-period signals includes: (7i) means to controllably vary the value of said digital time-period signals.

Claim 9

The circuit of claim 1, wherein said third means includes: (8i) settable voltage output means providing a "zero" reference time point (T 0 ) to a first analog comparator; (8ii) and wherein said fourth means includes: (8i-1) a first analog comparator to sense equality of said settable voltage with said ramp voltage to establish the time (T 0 ).

Claim 10

The circuit of claim 8, wherein said fifth means includes: (9i) a second analog comparator for sensing voltage equality between the output of said second means and said ramp voltage to establish the time (T 1 ), said second comparator then functioning to start said second output clock signal.

Claim 11

The circuit of claim 8, wherein the delay (d i ) between said first clock output signal and second clock output signal is period between time (T 0 ) and time (T 1 ).

Claim 12

A dual clocking circuit providing a variable delay period between first and second clock signals, said dual clocking delay circuit comprising: (a) a master reference clock for clocking a digital down counter and a capacitor bank; (b) a digital down counter clocked by said reference clock and providing variable time signals to a digital-analog converter; (c) first comparator means including: (c1) a reference voltage input; (c2) a ramp voltage input; (c3) a first clocking signal output; (d) second comparator means including: (d1) a time period-referenced analog voltage input; (d2) a ramp voltage input; (d3) a second clocking signal output; (e) digital-analog conversion means for converting a digital time period signal into an analog signal for input to said second comparator means; (f) ramp voltage generation means including: (f1) an adjustable constant current source for energizing a ramp-voltage line; (f2) a capacitor bank connected to said ramp-voltage line and energized by said reference clock; (f3) a ramp voltage output line connected to said adjustable constant current source and said capacitor bank and providing a ramp voltage output signal to said first and second analog comparators; and wherein said second clocking signal is activated in a time delayed period after said first clocking signal.

Claim 13

A dual clocking circuit providing a variable delay period between first and second clock signals, said dual clocking delay circuit comprising: (a) a master reference clock for clocking a digital down counter and a capacitor bank; (b) a digital down counter clocked by said reference clock and providing variable time signals to a digital-analog converter; (c) first comparator means including: (c1) a reference voltage input; (c2) a ramp voltage input; (c3) a first clocking signal output; (d) second comparator means including: (d1) a time period-referenced analog voltage input; (d2) a ramp voltage input; (d3) a second clocking signal output; (e) digital-analog conversion means for converting a digital time period signal into an analog signal for input to said second comparator means; (f) ramp voltage generation means including: (f1) an adjustable constant current source for energizing a ramp-voltage line; (f2) a capacitor bank connected to said ramp-voltage line and energized by said reference clock; (f3) a ramp voltage output line connected to said adjustable constant current source and said capacitor bank and providing a ramp voltage output signal to said first and second analog comparators; and wherein said second clocking signal is activated in a time delayed period after said first clocking signal.