Clock pulse driver

Claim 2

A current mode clock pulse driver for producing n individually enabled first clock pulse signals, p second clock pulse signals, and q third clock pulse signals where n, p and q are integers other than zero, all signals having two values denoted 0 and 1; said driver comprising: circuit means for receiving a system clock pulse signal, a first delay signal for said first signals, a second delay signal for said second signals, a third delay signal for said third signals, and n enable signals, one for each of the first clock pulse signals produced; circuit means for producing each of the n first clock signals at a time at which the enable signal for each of the n first clock signals and the system clock pulse signal and the first delay signal, each have a predetermined value; circuit means for producing p second clock signals at a time at which the second delay signal and the inverted system clock signal have a predetermined value; and circuit means for producing q third clock signals at a time at which the third delay signal and the inverted system clock signal have a predetermined value.

Claim 3

The clock pulse driver of claim 1 in which n=8, p=4 and q=4.

Claim 4

The clock pulse driver of claim 2 in which the predetermined value for the enable signal, the system clock pulse value and the first delay signal is that denoted 1.

Claim 5

The clock pulse driver of claim 3 in which the predetermined value for the second and third delay signal and the inverted system clock signal is that denoted 1.

Claim 6

A clock pulse driver for producing n individually enabled digital write clock pulse signals, n/2 first digital register clock pulse signals, and n/2 second digital register clock pulse signals from a system clock pulse signal where n is an even integer other than 0, said pulse signals having two values, a logical zero and a logical 1, each pulse of said pulse signals having a leading edge and a trailing edge, comprising: first circuit means for receiving said system clock pulse signal, a voltage reference signal, a delay write signal, a first delay register clock signal, a second delay register signal, and n write enable signals, said first circuit means producing n write clock pulse signals at a time at which the clock signal, the delay write signal and the write enable signals have predetermined logic values; said first circuit means producing the n/2 first register clock pulse signals at a time at which the system clock signal and the first delay register signal have predetermined logic value; and said first circuit means producing the n/2 second register clock pulse signals at a time at which the clock signal and the second delay register signal have predetermined logic values; and circuit means for producing a second clock pulse signal substantially in phase with the clock signal, and a plurality of delayed clock signals which are substantially 180 out of phase with the clock pulse signal, each such delayed clock signal being a delay write signal, a first delay register signal or a second delay register signal.

Claim 7

A clock pulse driver for producing n individually enabled digital write clock pulse signals, n/2 first digital register clock pulse signals, and n/2 second digital register clock pulse signals from a system clock pulse signal where n is an even integer other than 0, said pulse signals having two values, a logical zero and a logical 1, each pulse of said pulse signals having a leading edge and a trailing edge, comprising: first circuit means for receiving said system clock pulse signal, a voltage reference signal, a delay write signal, a first delay register clock signal, a second delay register signal, and n write enable signals, said first circuit means producing n write clock pulse signals at a time at which the clock signal, the delay write signal and the write enable signals have predetermined logic values; said first circuit means producing the n/2 first register clock pulse signals at a time at which the system clock signal and the first delay register signal have predetermined logic value; and said first circuit means producing the n/2 second register clock pulse signals at a time at which the clock signal and the second delay register signal have predetermined logic values; and circuit means for producing a second clock pulse signal substantially in phase with the clock signal, and a plurality of delayed clock signals which are substantially 180 out of phase with the clock pulse signal, each such delayed clock signal being a delay write signal, a first delay register signal or a second delay register signal.

Claim 8

The clock pulse driver of claim 5 in which n=8.

Claim 9

A current mode clock pulse driver for producing n individually enabled digital write clock pulse signals WP(1-n); n/2 digital register clock pulse signals RP((n/2-1)-1) from a digital clock signal $ where n is an even integer other than 0, said pulse signals having two values, a logical zero and a logical 1, each pulse of each of said signals having a leading edge and a trailing edge, comprising: first circuit means for receiving said clock signal $, a voltage reference signal VRef, a delay write signal DWP, a nonfunctional test signal, NFTS, a first delay register clock signal DRP(1-n/2), a second delay register signal DRP (n/2-1)-n and n write enable signals EW(1-n), said first circuit means producing said write clock pulse signals WP(1-n) at a time at which the following logic equation is satisfied: WP(n)=EW(n)·NFTS·DWP·$ said register clock pulse signals RP(1-n/2) at a time at which the following logic equation is satisfied: RP(1-n/2)=DRP(1-n/2)·$ and said register clock pulse signal RP((n/2+1)-n at a time at which the following logic equation is satisfied: RP((N/2+1-n)=DRP((n/2+1)-n)·$; and circuit means for producing a clock pulse RP0 substantially in phase with the clock signal $ and a plurality of delayed clock signals Tp which are substantially in phase with the inverted clock pulse $ and in which p equals an integer other than zero; each of said delay clock signal Tp having its leading edge delayed a different period of time relative to the leading edges of the pulses of said clock signal $.

Claim 10

A current mode clock pulse driver for producing n individually enabled digital write clock pulse signals WP(1-n); n/2 digital register clock pulse signals RP((n/2-1)-1) from a digital clock signal $ where n is an even integer other than 0, said pulse signals having two values, a logical zero and a logical 1, each pulse of each of said signals having a leading edge and a trailing edge, comprising: first circuit means for receiving said clock signal $, a voltage reference signal VRef, a delay write signal DWP, a nonfunctional test signal, NFTS, a first delay register clock signal DRP(1-n/2), a second delay register signal DRP (n/2-1)-n and n write enable signals EW(1-n), said first circuit means producing said write clock pulse signals WP(1-n) at a time at which the following logic equation is satisfied: WP(n)=EW(n)·NFTS·DWP·$ said register clock pulse signals RP(1-n/2) at a time at which the following logic equation is satisfied: RP(1-n/2)=DRP(1-n/2)·$ and said register clock pulse signal RP((n/2+1)-n at a time at which the following logic equation is satisfied: RP((N/2+1-n)=DRP((n/2+1)-n)·$; and circuit means for producing a clock pulse RP0 substantially in phase with the clock signal $ and a plurality of delayed clock signals Tp which are substantially in phase with the inverted clock pulse $ and in which p equals an integer other than zero; each of said delay clock signal Tp having its leading edge delayed a different period of time relative to the leading edges of the pulses of said clock signal $.

Claim 11

The current mode clock pulse driver of claim 7 in which n=8 and p=3.