US4223392A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clock-signal generator for a data-processing system
Assignee: Compagnie Internationale pour l'Informatique CII-Honeywell Bull SA
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Filing: 1978-01-31
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Granted: 1980-09-16
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Expires: 1998-01-31
Abstract
Abstract A plurality of sub-clock signals are derived from a main clock signal source by advancing a shift register and a counter with pulses from the main clock source. The shift register is selectively loaded with a desired combination of sub-clock bits in response to a predetermined number of main clock pulses being supplied to the counter. The sub-clock signals are derived from output terminals at different stages of the shift register. The state of the sub-clock signals can be selectively frozen by decoupling pulses from the main clock source to inputs of the counter and shift register.
Inventors
- 👤 Francis Lemaire
- 👤 Pierre Salkazanov
- 👤 Robert Bavoux
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 16:08
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
185 words
An apparatus for enabling a plurality of like-frequency sub-clock signals having differing phases to be generated from a main clock signal generator comprising: a first setting and logging means for indicating a state of the sub-clock signals in the form of multibit information; a second means having: a multiple taps memory means for storing the state of the sub-clock signals as logged by the said first means, means for shifting the state of the sub-clock signals stored in said memory means, and output means responsive to signals at the multiple taps of the memory means for deriving the sub-clock signals; a third means for controlling the shifting of the sub-clock signal state contained in the said second means by one bit for each cycle of the main clock signal; and a fourth means controlled by the main clock signal generator for counting the number of shifts of the sub-clock states in said second means, and means responsive to a predetermined count of the number of shifts for controlling the loading into the second means the state of the sub-clock signals indicated by the first means.
Claim 2
Independent Claim
185 words
An apparatus for enabling a plurality of like-frequency sub-clock signals having differing phases to be generated from a main clock signal generator comprising: a first setting and logging means for indicating a state of the sub-clock signals in the form of multibit information; a second means having: a multiple taps memory means for storing the state of the sub-clock signals as logged by the said first means, means for shifting the state of the sub-clock signals stored in said memory means, and output means responsive to signals at the multiple taps of the memory means for deriving the sub-clock signals; a third means for controlling the shifting of the sub-clock signal state contained in the said second means by one bit for each cycle of the main clock signal; and a fourth means controlled by the main clock signal generator for counting the number of shifts of the sub-clock states in said second means, and means responsive to a predetermined count of the number of shifts for controlling the loading into the second means the state of the sub-clock signals indicated by the first means.
Claim 3
Dependent Claim
25 words
The apparatus of claim 1 further comprising fifth means for enabling the sub-clock signals to be frozen in any state defined by said first means.
Claim 4
Dependent Claim
30 words
The apparatus of claim 2 wherein said first means comprises a series of amplifiers, each of which logs one bit of binary information representing the state of the sub-clock signals.
Claim 5
Dependent Claim
76 words
The apparatus of claim 1 wherein said second means comprises a feedback shift register, a decoder connected to the shift register for controlling the ability of the shift register to shift and for selecting the cycle of the main clock signal during which a sub-clock signal state set by the first means is loaded into the shift register and for enabling main clock signal cycles during which shifts are to take place in the shift register.
Claim 6
Dependent Claim
44 words
The apparatus of claim 1 wherein said fourth means comprises a counter responsive to the main clock signal and which counts in synchronization with the main clock signal, said counter having outputs connected to the inputs of a decoder included in said third means.
Claim 7
Dependent Claim
127 words
Apparatus for enabling a plurality of like-frequency sub-clock signals having differing phases to be generated from a main clock signal, comprising a shift register having a predetermined number of cascaded stages responsive to the main clock signal so signals are shifted between the stages in synchronization with the main clock signal, the sub-clock signals being derived from outputs of the shift register stages, means for enabling a coded signal for the different sub-clock signals to be selectively loaded into the shift register stages, and a counter responsive to the main clock signal so the counter is advanced in synchronism with the main clock signal, and a decoder responsive to a predetermined count of the counter for controlling the loading of the coded signal into said shift register.
Claim 8
Dependent Claim
127 words
Apparatus for enabling a plurality of like-frequency sub-clock signals having differing phases to be generated from a main clock signal, comprising a shift register having a predetermined number of cascaded stages responsive to the main clock signal so signals are shifted between the stages in synchronization with the main clock signal, the sub-clock signals being derived from outputs of the shift register stages, means for enabling a coded signal for the different sub-clock signals to be selectively loaded into the shift register stages, and a counter responsive to the main clock signal so the counter is advanced in synchronism with the main clock signal, and a decoder responsive to a predetermined count of the counter for controlling the loading of the coded signal into said shift register.
Claim 9
Dependent Claim
38 words
The apparatus of claim 6 further including a gate responsive to an external signal source for controlling freezing of the shift register at the sub-clock signal combination which has been loaded into the shift register by the decoder.
Claim 10
Dependent Claim
28 words
The apparatus of claim 7 wherein the gate is responsive to the simultaneous derivation of signals from the external signal source and decoder for freezing the shift register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-09-16 | 1984-03-17 | 1984-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-09-16 | 1988-03-17 | 1988-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-09-16 | 1992-03-17 | 1992-09-16 | $7700.00 | Window Closed / Lapsed |