Multimaster CPU system with early memory addressing

Claim 1

A data processing system comprising in combination: a. a plurality of central processing units interconnected via a bus; b. a plurality of memory units interconnected via said bus to said central processing units; and c. at least one of said memory units comprising a sequential memory address generator and said at least one of said memory units being enabled by a single one of said plurality of central processing units and having a means to receive and store a first memory address and a second subsequent memory address, respectively, therefrom, wherein said at least one memory unit further comprises: i. a sequential and artificial memory address generator for generating a sequential memory address, which is a single least significant bit different from said first memory address received, and directly applying said sequential memory address to said memory in anticipation of receipt of said second memory address from one of said plurality of central processing units; ii. means for comparing said second received memory address from one of said plurality of central processing units to said sequentially generated memory address; and iii. means for allowing said direct application of said sequential memory address to continue as a function of a correct compare of said second received memory address with said sequentially generated memory address.