US4032896A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microprocessor having index register coupled to serial-coupled address bus sections and to data bus
Assignee: Motorola Solutions Inc
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Filing: 1975-09-17
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Granted: 1977-06-28
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Expires: 1995-09-17
Abstract
Abstract A method of generating addresses in a microprocessor includes steps of storing first informationrepresentative of a first address in a first register, such as a program counter register. The first information is transmitted to a first address bus in order to effect addressing the contents of a first location represented by the first address. The first information is also transmitted via the address bus to an incrementor-decrementor circuit. The first information is incremented to produce second information representative of the address of the next instruction during the addressing of the first location. The second information is then transmitted to the first register.
Inventors
- 👤 Thomas H. Bennett
- 👤 Earl F. Carlow
- 👤 Anthony E. Kouvoussis
- 👤 Rodney H. Orgill
- 👤 Charles Peddle
- 👤 Michael F. Wiles
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:43
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/342; G06F15/00; G06F15/76; G06F15/78; G06F15/7828; G06F15/7832; G06F9/32; G06F9/321; G06F9/355; G06F9/3557
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
141 words
A method of operating a processor comprising the steps of: 1. storing first information representative of a first address in a first register and transmitting said first information to a first bus to effect addressing a first memory location represented by said first address, said first bus being an address bus; 2. transmitting said first information representative of said first address by means of said first bus to an arithmetic means and temporarily retaining said first information in said arithmetic means; 3. modifying said retained first information by means of said arithmetic means during said addressing of said first location to obtain second information representative of a second address; 4. reading information from or writing information into said first memory location by means of a data bus, depending on whether a read operation or a write operation is to be executed;
Claim 2
Independent Claim
141 words
A method of operating a processor comprising the steps of: 1. storing first information representative of a first address in a first register and transmitting said first information to a first bus to effect addressing a first memory location represented by said first address, said first bus being an address bus; 2. transmitting said first information representative of said first address by means of said first bus to an arithmetic means and temporarily retaining said first information in said arithmetic means; 3. modifying said retained first information by means of said arithmetic means during said addressing of said first location to obtain second information representative of a second address; 4. reading information from or writing information into said first memory location by means of a data bus, depending on whether a read operation or a write operation is to be executed;
Claim 3
Dependent Claim
98 words
transmitting said second information to said first register; 6. transmitting said second information to said first bus from said first register to effect addressing a second memory location represented by said second information; 7. transmitting said first information from said first bus to a second bus by means of switching means coupling said first and second buses during said addressing of said first location; and 8. performing an arithmetic operation on said first information on said second bus and third information present on said data bus prior to said transmitting of said second information to said first bus.
Claim 4
Dependent Claim
98 words
transmitting said second information to said first register; 6. transmitting said second information to said first bus from said first register to effect addressing a second memory location represented by said second information; 7. transmitting said first information from said first bus to a second bus by means of switching means coupling said first and second buses during said addressing of said first location; and 8. performing an arithmetic operation on said first information on said second bus and third information present on said data bus prior to said transmitting of said second information to said first bus.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-06-27 | 1980-12-27 | 1981-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-06-27 | 1984-12-27 | 1985-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-06-27 | 1988-12-27 | 1989-06-28 | $7700.00 | Window Closed / Lapsed |