Memory accessing method

Claim 2

In a computer system which includes a central processing unit (CPU) and a dynamic memory which requires periodic refresh cycles, where said CPU provides an access signal to said memory when said memory is to be accessed and accesses data from said memory synchronized with a control clock signal after receipt of a ready signal, and wherein said memory provides a data valid signal to indicate that data is ready for reading and an advanced data valid signal which indicates that the memory is being accessed without collision with said refresh cycles, an improved method for accessing data from said memory comprising the steps of: initiating a timing sequence based on the occurrences of said access signal from said CPU; allowing said timing sequence to continue if said advanced data valid signal is present during said timing sequence; and, generating said ready signal at the end of said timing sequence, whereby the time required to access data is shortened when refresh cycles are not occurring.

Claim 3

The method defined by claim 1 wherein said ready signal is generated without regard to said data valid signal.

Claim 4

The method defined by claim 2 wherein said timing sequence includes the generation of a pulse of predetermined width generated in synchronous with said control clock.

Claim 5

The method defined by claim 3 wherein said ready signal is generated at the end of said pulse.

Claim 6

The method defined by claim 1 wherein said ready signal is generated in response to said data valid signal if said timing sequence is interrupted because of the absence of said advanced data signal.

Claim 7

In a computer system which includes a central processing unit (CPU) and a dynamic memory both of which are coupled to a bus, where said CPU provides an access signal such as memory-read and memory-write to said memory when said memory is to be accessed and senses data on said bus synchronized with control clock signals after receipt of a ready signal from a clock generator, and wherein said memory provides an acknowledge signal (XACK) to indicate that data has been coupled to said bus and an advanced acknowledge signal (AACK) to indicate that the memory is being accessed without collision with a refresh cycles needed to refresh said dynamic memory, an improved method for accessing data from said memory comprising the steps of: initiating a logic sequence of predetermined duration synchronized with said control clock signals on the occurrence of said access signal from said CPU; determining if said AACK signal is present; allowing said logic sequence to continue if said AACK signal is present; and, generating said ready signal at the end of said logic sequence, whereby the time required to access data is shortened when refresh cycles are not occurring.

Claim 8

In a computer system which includes a central processing unit (CPU) and a dynamic memory both of which are coupled to a bus, where said CPU provides an access signal such as memory-read and memory-write to said memory when said memory is to be accessed and senses data on said bus synchronized with control clock signals after receipt of a ready signal from a clock generator, and wherein said memory provides an acknowledge signal (XACK) to indicate that data has been coupled to said bus and an advanced acknowledge signal (AACK) to indicate that the memory is being accessed without collision with a refresh cycles needed to refresh said dynamic memory, an improved method for accessing data from said memory comprising the steps of: initiating a logic sequence of predetermined duration synchronized with said control clock signals on the occurrence of said access signal from said CPU; determining if said AACK signal is present; allowing said logic sequence to continue if said AACK signal is present; and, generating said ready signal at the end of said logic sequence, whereby the time required to access data is shortened when refresh cycles are not occurring.

Claim 9

The method defined by claim 6 wherein said ready signal is generated without regard to the XACK signal when said AACK signal is present.

Claim 10

The method defined by claim 7 wherein said ready signal is generated in response to said XACK signal when said AACK signal is not present during said predetermined duration.

Claim 11

The method defined by claim 8 wherein said logic sequence includes the generation of a pulse of predetermined width and wherein said ready signal is generated at the end of said pulse.

Claim 12

The method defined by claim 9 wherein said ready signal is generated in synchronous with said control clock signal and wherein said data is sensed on said bus on the occurrence of the next clock signal after said ready signal.